Software and hardware development for C-V analysis of MOS capacitors for a laboratory course in process evaluation

Hardware and software for data extraction from MOS capacitors via C-V analysis are described. Guidelines for minimizing and/or correcting noise, series resistance, leakage current, and parasitic capacitances in experimental apparatus are presented. A Fortran program for generating model 1 MHz and quasi-static C-V plots was written. By contrasting experimental curves to theory, the program extracts flatband voltage shift, oxide thickness, substrate doping, and interface traps. Examples of applications in theoretical discussions and IC process characterization are given.<<ETX>>