Diagnosing single faults for interconnects in SRAM based FPGAs

This paper presents a method to diagnose faults in FPGA interconnection resources. A single fault model is given. Under the given model, a diagnosing method is proposed. At most five programming steps in the proposed method is required if adaptive testing scheme is used. For non-adaptive test, eight programming steps is required to diagnose all the possible faults under the given single fault model. The accuracy of the fault diagnosing is one segment for a segment stuck-at or stuck-open fault, a segment pair for a bridge fault, a switch for switch stuck-on or stuck-off fault.

[1]  Yervant Zorian,et al.  Testing the Interconnect of RAM-Based FPGAs , 1998, IEEE Des. Test Comput..

[2]  Hideo Fujiwara,et al.  Testing for the programming circuit of LUT-based FPGAs , 1997, Proceedings Sixth Asian Test Symposium (ATS'97).

[3]  Fabrizio Lombardi,et al.  On the diagnosis of programmable interconnect systems: Theory and application , 1996, Proceedings of 14th VLSI Test Symposium.

[4]  William H. Kautz,et al.  Testing for Faults in Wiring Networks , 1974, IEEE Transactions on Computers.

[5]  Hideo Fujiwara,et al.  Universal test complexity of field-programmable gate arrays , 1995, Proceedings of the Fourth Asian Test Symposium.