Microkernel Architecture and Hardware Abstraction Layer of a Reliable Reconfigurable Real-Time Operating System (R3TOS)

This article presents a new solution for easing the development of reconfigurable applications using Field-Programable Gate Arrays (FPGAs). Namely, our Reliable Reconfigurable Real-Time Operating System (R3TOS) provides OS-like support for partially reconfigurable FPGAs. Unlike related works, R3TOS is founded on the basis of resource reusability and computation ephemerality. It makes intensive use of reconfiguration at very fine FPGA granularity, keeping the logic resources used only while performing computation and releasing them as soon as it is completed. To achieve this goal, R3TOS goes beyond the traditional approach of using reconfigurable slots with fixed boundaries interconnected by means of a static communication infrastructure. Instead, R3TOS approaches a static route-free system where nearly everything is reconfigurable. The tasks are concatenated to form a computation chain through which partial results naturally flow, and data are exchanged among remotely located tasks using FPGA’s reconfiguration mechanism or by means of “removable” routing circuits. In this article, we describe the R3TOS microkernel architecture as well as its hardware abstraction services and programming interface. Notably, the article presents a set of novel circuits and mechanisms to overcome the limitations and exploit the opportunities of Xilinx reconfigurable technology in the scope of hardware multitasking and dependability.

[1]  Jim Tørresen,et al.  Go Ahead: A Partial Reconfiguration Framework , 2012, 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines.

[2]  Ulrich Rückert,et al.  REPLICA: a bitstream manipulation filter for module relocation in partial reconfigurable systems , 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

[3]  Abdulazim Amouri,et al.  A Low-Cost Sensor for Aging and Late Transitions Detection in Modern FPGAs , 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

[4]  Charles E. Stroud,et al.  Online BIST and BIST-based diagnosis of FPGA logic blocks , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Enno Lübbers.  Multithreaded Programming and Execution Models for Reconfigurable Hardware , 2010 .

[6]  Jürgen Becker,et al.  Operating System for Runtime Reconfigurable Multiprocessor Systems , 2011, Int. J. Reconfigurable Comput..

[7]  Fabrice Muller,et al.  A Flexible Operating System for Dynamic Applications , 2010 .

[8]  Jim Tørresen,et al.  High Speed Partial Run-Time Reconfiguration Using Enhanced ICAP Hard Macro , 2011, 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum.

[9]  John A. Williams,et al.  A Process Model for Hardware Modules in Reconfigurable System-on-Chip , 2006, ARCS.

[10]  Marco Caccamo,et al.  Adaptive Allocation of Software and Hardware Real-Time Tasks for FPGA-based Embedded Systems , 2006, 12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'06).

[11]  L. Sterpone,et al.  Analysis of the robustness of the TMR architecture in SRAM-based FPGAs , 2005, IEEE Transactions on Nuclear Science.

[12]  Jürgen Teich,et al.  Task scheduling for heterogeneous reconfigurable computers , 2004, Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784).

[13]  Lesley Shannon,et al.  FUSE: Front-End User Framework for O/S Abstraction of Hardware Accelerators , 2011, 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines.

[14]  Christian Haubelt,et al.  Efficient Reconfigurable On-Chip Buses for FPGAs , 2008, 2008 16th International Symposium on Field-Programmable Custom Computing Machines.

[15]  Tian Xia,et al.  An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults , 2006, J. Electron. Test..

[16]  Mark Jones,et al.  Metawire: Using FPGA configuration circuitry to emulate a Network-on-Chip , 2008, 2008 International Conference on Field Programmable Logic and Applications.

[17]  Rudy Lauwereins,et al.  Infrastructure for design and management of relocatable tasks in a heterogeneous reconfigurable system-on-chip , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[18]  Peter M. Athanas,et al.  OpenPR: An Open-Source Partial-Reconfiguration Toolkit for Xilinx FPGAs , 2011, 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum.

[19]  Robert W. Brodersen,et al.  Borph: an operating system for fpga-based reconfigurable computers , 2007 .

[20]  John D. Corbett.  The Xilinx Isolation Design Flow for Fault-Tolerant Systems , 2013 .

[21]  Marco D. Santambrogio,et al.  Internal and External Bitstream Relocation for Partial Dynamic Reconfiguration , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[22]  Hermann Kopetz,et al.  Real-time systems , 2018, CSC '73.

[23]  Jürgen Teich,et al.  DyNoC: A dynamic infrastructure for communication in dynamically reconfugurable devices , 2005, International Conference on Field Programmable Logic and Applications, 2005..

[24]  Tughrul Arslan,et al.  Online clock routing in Xilinx FPGAs for high-performance and reliability , 2012, 2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

[25]  John A. Williams,et al.  FIFO communication models in operating systems for reconfigurable computing , 2005, 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05).

[26]  Adam Donlin,et al.  A Virtual File System for Dynamically Reconfigurable FPGAs , 2004, FPL.

[27]  Tughrul Arslan,et al.  Efficient On-Chip Task Scheduler and Allocator for Reconfigurable Operating Systems , 2011, IEEE Embedded Systems Letters.

[28]  Raúl Torrego.  OQPSK COGNITIVE MODULATOR FULLY FPGA-IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS , 2011 .

[29]  Jürgen Becker,et al.  Message Passing Interface support for the runtime adaptive multi-processor system-on-chip RAMPSoC , 2010, ICSAMOS.

[30]  Jürgen Teich,et al.  ReCoBus-Builder — A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS , 2008, 2008 International Conference on Field Programmable Logic and Applications.

[31]  Tughrul Arslan,et al.  Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence , 2013, Int. J. Reconfigurable Comput..

[32]  Jens Sparsø,et al.  ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology , 2008, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008).

[33]  Shantanu Dutt,et al.  Built-in-Self-Test of FPGAs With Provable Diagnosabilities and High Diagnostic Coverage With Application to Online Testing , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[34]  K. Chapman.  SEU Strategies for Virtex-5 Devices , 2010 .

[35]  Wayne Luk,et al.  Run-Time Integration of Reconfigurable Video Processing Systems , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[36]  Heiko Kalte,et al.  Context saving and restoring for multitasking in reconfigurable systems , 2005, International Conference on Field Programmable Logic and Applications, 2005..

[37]  Tughrul Arslan,et al.  Methods and Mechanisms for Hardware Multitasking: Executing and Synchronizing Fully Relocatable Hardware Tasks in Xilinx FPGAs , 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

[38]  Gordon J. Brebner,et al.  A Virtual Hardware Operating System for the Xilinx XC6200 , 1996, FPL.

[39]  Fearghal Morgan,et al.  Run-Time Management of Reconfigurable Hardware Tasks Using Embedded Linux , 2007, 2007 International Conference on Field-Programmable Technology.

[40]  Hideharu Amano,et al.  A Method for Capturing State Data on Dynamically Reconfigurable Processors , 2008, ERSA.

[41]  Khaled Benkrid,et al.  A novel high-performance fault-tolerant ICAP controller , 2012, 2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

[42]  Bo Zhou,et al.  An operating system framework for reconfigurable systems , 2005, The Fifth International Conference on Computer and Information Technology (CIT'05).

[43]  Hiroaki Takada,et al.  A Novel Mechanism for Effective Hardware Task Preemption in Dynamically Reconfigurable Systems , 2010, 2010 International Conference on Field Programmable Logic and Applications.

[44]  Khaled Benkrid,et al.  Multiple-clone configuration of relocatable partial bitstreams in Xilinx Virtex FPGAs , 2013, 2013 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2013).

[45]  Tughrul Arslan,et al.  Snake: An Efficient Strategy for the Reuse of Circuitry and Partial Computation Results in High-Performance Reconfigurable Computing , 2011, 2011 International Conference on Reconfigurable Computing and FPGAs.

[46]  Jürgen Teich,et al.  A practical approach for circuit routing on dynamic reconfigurable devices , 2005, 16th IEEE International Workshop on Rapid System Prototyping (RSP'05).

[47]  Marco D. Santambrogio,et al.  Operating system support for online partial dynamic reconfiguration management , 2008, 2008 International Conference on Field Programmable Logic and Applications.

[48]  Jim Tørresen,et al.  Obstacle-free two-dimensional online-routing for run-time reconfigurable FPGA-based systems , 2010, 2010 International Conference on Field-Programmable Technology.

[49]  Jon Perez,et al.  R3TOS: A Novel Reliable Reconfigurable Real-Time Operating System for Highly Adaptive, Efficient, and Dependable Computing on FPGAs , 2013, IEEE Transactions on Computers.

[50]  Camel Tanougast,et al.  A Hardware Preemptive Multitasking Mechanism Based on Scan-path Register Structure for FPGA-based Reconfigurable Systems , 2007, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007).

[51]  D. Andrews,et al.  hthreads: a hardware/software co-designed multithreaded RTOS kernel , 2005, 2005 IEEE Conference on Emerging Technologies and Factory Automation.

[52]  Fabrizio Ferrandi,et al.  Operating system support for dynamically reconfigurable SoC architectures , 2005, Proceedings 2005 IEEE International SOC Conference.

[53]  Heiko Kalte,et al.  REPLICA2Pro: task relocation by bitstream manipulation in virtex-II/Pro FPGAs , 2006, CF '06.

[54]  Ann Gordon-Ross,et al.  VAPRES: A Virtual Architecture for Partially Reconfigurable Embedded Systems , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[55]  Mikel Azkarate-askasua,et al.  A novel SEU, MBU and SHE handling strategy for Xilinx Virtex-4 FPGAs , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[56]  Neil W. Bergmann,et al.  Embedded Linux as a Platform for Dynamically Self-Reconfiguring Systems-on-Chip , 2004, ERSA.

[57]  Michael J. Wirthlin,et al.  FPGA partial reconfiguration via configuration scrubbing , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[58]  Herbert H. Walder.  Operating System Design for Partiallly Reconfigurable Logic Devices , 2005 .

[59]  P. Athanas,et al.  Untethered On-The-Fly Radio Assembly With Wires-On-Demand , 2008, 2008 IEEE National Aerospace and Electronics Conference.

[60]  Reinhard Männer,et al.  Multitasking on FPGA Coprocessors , 2000, FPL.

[61]  Philip James-Roxby,et al.  A Self-reconfiguring Platform , 2003, FPL.

[62]  Christian Haubelt,et al.  Efficient hardware checkpointing: concepts, overhead analysis, and implementation , 2007, FPGA '07.