A self-control technique for high efficiency class-E CMOS power amplifier

In this paper, a self-control (SC) technique for high efficiency class-E CMOS power amplifier is presented for GSM standard. Cascode topology due to high sustainability of voltage stress is mostly considered in CMOS PAs, but slow transition of common-gate device from triode to cut-off region is the most problematic issue of cascode configuration and the main source of power loss. In order to minimize its power loss a positive feedback technique is used. The proposed technique speeds up on-to-off and off-to-on transition time and lower the on and off drain's voltage of the common-gate device. Therefore, the common-gate device turns off and on instantly after common-source device in lower drain voltage and consequently the technique shows an improvement in the overall performance of the PA. To demonstrate its performance a self-control class-E CMOS PA has been designed, simulate, and compared to conventional class-E CMOS PA. It has shown that more than 2% improvement is achieved in power-added efficiency (PAE). Under a 3.3V power supply, the proposed CMOS PA in 0.18um CMOS process at 1.8GHz gives 29.6dBm output power.