Mixed-Signal Testing and DfT

[1]  Degang Chen,et al.  Linearity testing of precision analog-to-digital converters using stationary nonlinear inputs , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[2]  Yvon Savaria,et al.  Tools for the characterization of bipolar CML testability , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[3]  David Keezer,et al.  Modular extension of ATE to 5 Gbps , 2004 .

[4]  André Ivanov,et al.  Embedded timing analysis: a soc infrastructure , 2002, IEEE Design & Test of Computers.

[5]  Naim Ben Hamida,et al.  LIMSoft : automated tool for sensitivity analysis and test vector generation : Mixed signal & analogue IC test technology , 1996 .

[6]  Karim Arabi,et al.  Testing analog and mixed-signal integrated circuits using oscillation-test method , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Matthew Mahoney,et al.  DSP-Based Testing of Analog and Mixed-Signal Circuits , 1987 .

[8]  Robert C. Aitken,et al.  THE EFFECT OF DIFFERENT TEST SETS ON QUALITY LEVEL PREDICTION: WHEN IS 80% BETTER THAN 90%? , 1991, 1991, Proceedings. International Test Conference.

[9]  Solomon Max Testing high speed high accuracy analog to digital converters embedded in systems on a chip , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[10]  Abhijit Chatterjee,et al.  A high-resolution jitter measurement technique using ADC sampling , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[11]  Abhijit Chatterjee,et al.  Fault simulation of linear analog circuits , 1993, J. Electron. Test..

[12]  Abhijit Chatterjee,et al.  Prediction of analog performance parameters using fast transienttesting , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Gloria Huertas,et al.  Self-testable pipelined ADC with low hardware overhead , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[14]  Martin H. Graham,et al.  Book Review: High-Speed Digital Design: A Handbook of Black Magic by Howard W. Johnson and Martin Graham: (Prentice-Hall, 1993) , 1993, CARN.

[15]  Benoit Nadeau-Dostie,et al.  Complete, contactless I/O testing reaching the boundary in minimizing digital IC testing cost , 2002, Proceedings. International Test Conference.

[16]  J.-F. Cote,et al.  An automated, complete, structural test solution for SERDES , 2004 .

[17]  Gordon W. Roberts,et al.  Test and evaluation of multiple embedded mixed-signal test cores , 2002, Proceedings. International Test Conference.

[18]  Gordon W. Roberts,et al.  A BIST scheme for a SNR, gain tracking, and frequency response test of a sigma-delta ADC , 1995 .

[19]  T. R. Viswanathan,et al.  Integrated circuit testing for quality assurance in manufacturing: history, current status, and future trends , 1997 .

[20]  Stephen K. Sunter,et al.  A general purpose 1149.4 IC with HF analog test capabilities , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[21]  Abhijit Chatterjee,et al.  DC Built-In Self-Test for Linear Analog Circuits , 1996, IEEE Des. Test Comput..

[22]  Jeffrey K. Hollingsworth,et al.  Instrumentation and Measurement , 1998, 2022 International Symposium on Electronics and Telecommunications (ISETC).

[23]  Florence Azaïs,et al.  A low-cost adaptive ramp generator for analog BIST applications , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[24]  Alberto L. Sangiovanni-Vincentelli,et al.  Minimizing production test time to detect faults in analog circuits , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[25]  Aubin Roy,et al.  BIST for phase-locked loops in digital applications , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[26]  Thomas Almy,et al.  HABIST: histogram-based analog built in self test , 1997, Proceedings International Test Conference 1997.

[27]  Bozena Kaminska,et al.  BIST for D/A and A/D Converters , 1996, IEEE Des. Test Comput..

[28]  João Paulo Teixeira,et al.  Defect level evaluation in an IC design environment , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[29]  Helmut Graeb,et al.  Design based analog testing by characteristic observation inference , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[30]  Takahiro J. Yamaguchi,et al.  A method for measuring the cycle-to-cycle period jitter of high-frequency clock signals , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[31]  Kwang-Ting Cheng,et al.  Test generation for linear time-invariant analog circuits , 1999 .

[32]  Stephen K. Sunter,et al.  Test metrics for analog parametric faults , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[33]  P. P. Fasang,et al.  Design for testability for mixed analog/digital ASICs , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.

[34]  Stephen K. Sunter Testing high frequency adcs and dacs with a low frequency analog bus , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[35]  Gordon W. Roberts,et al.  An Introduction to Mixed-Signal IC Test and Measurement , 2000 .

[36]  Aubin Roy,et al.  High accuracy stimulus generation for A/D converter BIST , 2002, Proceedings. International Test Conference.

[37]  Edgar Sánchez-Sinencio,et al.  Auto-calibrating analog timer for on-chip testing , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[38]  Stig Oresjo,et al.  Structure and metrology for an analog testability bus , 1993, Proceedings of IEEE International Test Conference - (ITC).

[39]  Zhen Guo,et al.  Test limitations of parametric faults in analog circuits , 2003, IEEE Trans. Instrum. Meas..

[40]  Joan Figueras,et al.  Characterization of Floating Gate Defects in Analog Cells , 1999, J. Electron. Test..

[41]  Jacob A. Abraham,et al.  Analog Testing with Time Response Parameters , 1996, IEEE Des. Test Comput..

[42]  Manoj Sachdev A realistic defect oriented testability methodology for analog circuits , 1995, J. Electron. Test..

[43]  João Paulo Teixeira,et al.  Automatic fault extraction and simulation of layout realistic faults for integrated analogue circuits , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[44]  Gordon W. Roberts,et al.  Mixed-Signal Testing , 2000 .

[45]  Brown,et al.  Defect Level as a Function of Fault Coverage , 1981, IEEE Transactions on Computers.