Electrical and thermal scaling trends for SOI FinFET ESD design

This paper first presents an analysis of the holding voltage of NMOS and PMOS SOI FinFETs in bipolar mode. Further, to make FinFETs an area-efficient technology option, geometrical parameters which are fixed by the current process will be scaled down. A TCAD simulation methodology is used to predict the robustness of scaled-down FinFETs.