Electrical and thermal scaling trends for SOI FinFET ESD design
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R. Rooyackers | C. Duvvury | N. Collaert | D. Linten | D. Tremouilles | S. Thijs | A. Griffoni | G. Groeseneken | M. Scholz | C. Russ
[1] R. Rooyackers,et al. Doubling or quadrupling MuGFET fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficiency , 2006, 2006 International Electron Devices Meeting.
[2] R. Rooyackers,et al. Impact of Strain on ESD Robustness of FinFET Devices , 2008, 2008 IEEE International Electron Devices Meeting.
[3] C. Duvvury,et al. Understanding the optimization of sub-45nm FinFET devices for ESD applications , 2007, 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).
[4] Steve Hall,et al. Physical origin of negative differential resistance in SOI transistors , 1989 .
[5] S. L. Miller. Ionization Rates for Holes and Electrons in Silicon , 1957 .
[6] K. Ohuchi,et al. Impact of BOX scaling on 30 nm gate length FD SOI MOSFET , 2005, 2005 IEEE International SOI Conference Proceedings.
[7] C. Duvvury,et al. Esd in Silicon Integrated Circuits [Book Reviews] , 1997 .