Design and reliability analysis of a novel wafer level package with stress buffer mechanism
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[1] Leilei Zhang,et al. Effect of solder ball pad design on cavity down BGA solder joint reliability , 2002, 52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345).
[2] H. Solomon. Fatigue of 60/40 Solder , 1986 .
[3] L. L. Mercado,et al. Impact of solder pad size on solder joint reliability in flip chip PBGA packages , 1999, 1999 Proceedings. 49th Electronic Components and Technology Conference (Cat. No.99CH36299).
[4] P. Garrou,et al. Wafer level chip scale packaging (WL-CSP): an overview , 2000, ECTC 2000.
[5] Chih-Tang Peng,et al. Parametric reliability analysis of no-underfill flip chip package , 2001 .
[6] I. Anjoh,et al. Development of low-cost and highly reliable wafer process package , 2001, 2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).
[7] Jong-heon Kim,et al. The solder joint and runner metal reliability of wafer-level CSP (Omega-CSP) , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).
[8] S. Manson. Fatigue: A complex subject—Some simple approximations , 1965 .
[9] T. Mckeown. Mechanics , 1970, The Mathematics of Fluid Flow Through Porous Media.
[10] Kuo-Ning Chiang,et al. An overview of solder bump shape prediction algorithms with validations , 2001, ECTC 2001.
[12] L. L. Mercado,et al. Impact of solder pad size on solder joint reliability in flip chip PBGA packages , 2000 .
[13] Kuo-Ning Chiang,et al. On enhancing eutectic solder joint reliability using a second-reflow-process approach , 2000 .
[14] Nikhil Vishwanath Kelkar,et al. MicroSMD-a wafer level chip scale package , 2000, ECTC 2000.
[15] C.-H. Choi,et al. Thermo-mechanical behavior of elastomer for CSP and reliability , 2001, ISIE 2001. 2001 IEEE International Symposium on Industrial Electronics Proceedings (Cat. No.01TH8570).
[16] K. Chiang,et al. Solder joint reliability analysis of a wafer‐level CSP assembly with cu studs formed on solder pads , 2003 .
[17] A. Badihi,et al. Ultrathin wafer level chip size package , 2000, ECTC 2000.
[18] L. Coffin,et al. A Study of the Effects of Cyclic Thermal Stresses on a Ductile Metal , 1954, Journal of Fluids Engineering.
[19] Kuo-Ning Chiang,et al. Parametric Design and Reliability Analysis of Wire Interconnect Technology Wafer Level Packaging , 2002 .