Reversible Logic-Based Fault-Tolerant Nanocircuits in QCA

Parity-preserving reversible circuits are gaining importance for the development of fault-tolerant systems in nanotechnology. On the other hand, Quantum-dot Cellular Automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. This work targets design of reversible ALU (arithmetic logic unit) in QCA (Quantum-dot Cellular Automata) framework. The design is based on the fault tolerant reversible adders (FTRA) introduced in this paper. The proposed fault tolerant adder is a parity-preserving gate, and QCA implementation of FTRA achieved 47.38% fault-free output in the presence of all possible single missing/additional cell defects. The proposed designs are verified and evaluated over the existing ALU designs and found to be more efficient in terms of design complexity and quantum cost.

[1]  Xiaojun Ma,et al.  Fault Tolerant Schemes for QCA Systems , 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

[2]  Fabrizio Lombardi,et al.  Modeling QCA defects at molecular-level in combinational circuits , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

[3]  Wolfgang Porod,et al.  Quantum cellular automata , 1994 .

[4]  Zhijin Guan,et al.  An Arithmetic Logic Unit design based on reversible logic gates , 2011, Proceedings of 2011 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing.

[5]  Rolf Landauer,et al.  Irreversibility and heat generation in the computing process , 1961, IBM J. Res. Dev..

[6]  Muhammad Mahbubur Rahman,et al.  Efficient Approaches for Designing Fault Tolerant Reversible Carry Look-Ahead and Carry-Skip Adders , 2010, ArXiv.

[7]  Martin Lukac,et al.  A Hierarchical Approach to Computer-Aided Design of Quantum Circuits , 2003 .

[8]  Keivan Navi,et al.  A Novel Fault Tolerant Reversible Gate For Nanotechnology Based Systems , 2008 .

[9]  A. V. N. Tilak,et al.  Reversible Arithmetic Logic Unit , 2011, 2011 3rd International Conference on Electronics Computer Technology.

[10]  T.J. Dysart,et al.  > Replace This Line with Your Paper Identification Number (double-click Here to Edit) < 1 , 2001 .

[11]  Ahsan Raja Chowdhury,et al.  Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic Synthesis , 2012, 2012 25th International Conference on VLSI Design.

[12]  Mitchell A. Thornton,et al.  Efficient adder circuits based on a conservative reversible logic gate , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[13]  Tommaso Toffoli,et al.  Reversible Computing , 1980, ICALP.

[14]  Fabrizio Lombardi,et al.  HDLQ: A HDL environment for QCA design , 2006, JETC.

[15]  N. Ranganathan,et al.  Design of a Reversible ALU Based on Novel Programmable Reversible Logic Gate Structures , 2011, 2011 IEEE Computer Society Annual Symposium on VLSI.

[16]  Charles H. Bennett,et al.  Logical reversibility of computation , 1973 .

[17]  B. Parhami,et al.  Fault-Tolerant Reversible Circuits , 2006, 2006 Fortieth Asilomar Conference on Signals, Systems and Computers.

[18]  F. Lombardi,et al.  Testing of quantum cellular automata , 2004, IEEE Transactions on Nanotechnology.