DESIGN OF TEST STRUCTURE FOR 3D-STACKED INTEGRATED CIRCUITS (3D-SICS) METROLOGY | NIST

• A multi-level chip to simulate 3D circuit issues • Must be SPM friendly (SMM, KFM, SCM, etc.) • Provide multi-level subsurface structures • Can be externally biased and extract physical parameters (φ, E, B, C, ε, etc... ) Background • 3D Stacked Integrated Circuits (3D-SICs) draw tremendous research. 1 • However, it faces some challenges such as Through Silicon Vias (TSVs) and Back-end of line (BEOL) issues. 2-4 • Scanning Probe Microscopy (SPM) technologies have mature surface metrology capability but is short in subsurface imaging, which is important for 3D-SICs. • Recently, some SPM techniques show their capability of subsurface characterization on different semiconductor devices. 5, 6