Implementation of packet-fair queuing algorithms in high speed routers based on discrete rates and packet lengths group architectures

In this paper,we present an effective implementing architecture of packet fair queuing schedulers based on discrete backlogged rates and discrete packet lengths This architecture can flexibly provide different bandwidth granularities for various backlogged flow rates With the modularization design and pipeline technology,this architecture makes more efficient using of hardware resources We also provide a new technology of reconstructing flow timestamps for this architecture which can effectively decrease the storage space of timestamps Results of algorithm simulating and FPGA synthesizing show that this design can fully support a 1.2Gbit/s output link By the efficient combination of two 1 2Gbit/s schedulers,this design can be further capable of OC-48(2 4Gbit/s)operations in high speed routers