An on-chip, interconnect capacitance characterization method with sub-femto-farad resolution

In this paper, a sensitive and simple technique for parasitic interconnect capacitance measurement with 0.01 fF sensitivity is presented. This on-chip technique is based upon an efficient test structure design. No reference capacitor is needed. Only a DC current meter is required for its measurement. We have applied this technique to extract various interconnect geometry capacitances and compared the results to those from 3D simulations.

[1]  T. Sakurai,et al.  Simple formulas for two- and three-dimensional capacitances , 1983, IEEE Transactions on Electron Devices.

[2]  G. J. Gaston,et al.  Efficient extraction of metal parasitic capacitances , 1995, Proceedings International Conference on Microelectronic Test Structures.

[3]  H. Richter,et al.  A new method and test structure for easy determination of femto-farad on-chip capacitances in a MOS process , 1992, ICMTS 92 Proceedings of the 1992 International Conference on Microelectronic Test Structures.

[4]  Pascal Nouet,et al.  On-chip measurement of interconnect capacitances in a CMOS process , 1995, Proceedings International Conference on Microelectronic Test Structures.

[5]  C. Kortekaas.  On-chip quasi-static floating-gate capacitance measurement method , 1990, International Conference on Microelectronic Test Structures.

[6]  S.Y. Oh,et al.  3D GIPER: global interconnect parameter extractor for full-chip global critical path analysis , 1996, International Electron Devices Meeting. Technical Digest.

[7]  P. Nouet,et al.  A new test structure for interconnect capacitance monitoring , 1997, 1997 IEEE International Conference on Microelectronic Test Structures Proceedings.

[8]  Llanda M. Richardson,et al.  Modeling and extraction of interconnect capacitances for multilayer VLSI circuits , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Gabor C. Temes,et al.  Random error effects in matched MOS capacitors and current sources , 1984 .