Optimizing RLC tree delays by employing repeater insertion

The effects of inductance on repeater insertion in RLC trees is the focus of this paper. An algorithm is introduced to insert and size buffers within an RLC tree to minimize a variety of possible cost functions such as minimizing the maximum path delay, the skew, or a combination of area, power, and delay. The algorithm has a complexity proportional to the square of the number of possible buffer positions and determines a buffer solution that is close to the global minimum. The buffer insertion algorithm is used to insert buffers within several copper-based interconnect trees to minimize the maximum path delay based on both an RC model and an RLC model. The two buffering solutions are compared using the AS/X dynamic circuit simulator. It is shown that as inductance effects increase, the area and power consumed by the inserted buffers to minimize the path delays of an RLC tree decreases. By including inductance in the repeater insertion methodology, the interconnect is modeled more accurately as compared to an RC model, permitting average savings in area, power, and delay of 40.8%, 15.6%, and 6.7%, respectively, for a variety of copper-based interconnect trees for a 0.25 /spl mu/m CMOS technology. The average savings in area, power, and delay increases to 62.2%, 57.2%, and 9.4%, respectively, when using five times faster devices with the same interconnect trees.

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