Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect

Asynchronous design offers a solution to the interconnect problems faced by system-on-chip (SoC) designers, but their adoption has been held back by a lack of methodology and support for post-fabrication testing. This paper first addresses the problem of testing C-elements, an important building block of asynchronous circuits. A simple method for generating test patterns is described which is shown to be applicable for a wide range of implementations. Based on the C-element testability, a partial scan technique was developed that achieves a test coverage of over 99.5% when applied to an asynchronous, network-on-chip, interconnect fabric. Test patterns are automatically generated by a custom program, given the interconnect topology. Area savings of at least 60% are noted, in comparison to standard, asynchronous, full-scan level-sensitive scan devices (LSSD) methods.

[1]  Aristides Efthymiou,et al.  Adding testability to an asynchronous interconnect for GALS SoC , 2004, 13th Asian Test Symposium.

[2]  William B. Toms,et al.  Delay-insensitive, point-to-point interconnect using m-of-n codes , 2003, Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings..

[3]  Teresa H. Y. Meng,et al.  Semi-modularity and testability of speed-independent circuits , 1992, Integr..

[4]  Aristides Efthymiou,et al.  Automatic scan insertion and pattern generation for asynchronous circuits , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[5]  Thomas W. Williams,et al.  A logic design structure for LSI testability , 1977, DAC '77.

[6]  Michael Yoeli,et al.  SELF-TIMED is SELF-DIAGNOSTIC , 1995 .

[7]  Gaetano Borriello,et al.  Testing asynchronous circuits: A survey , 1995, Integr..

[8]  Marly Roncken,et al.  Optimal scan for pipelined testing: an asynchronous foundation , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[9]  Jim D. Garside,et al.  SPA - a synthesisable Amulet core for smartcard applications , 2002, Proceedings Eighth International Symposium on Asynchronous Circuits and Systems.

[10]  Aaas News,et al.  Book Reviews , 1893, Buffalo Medical and Surgical Journal.

[11]  Stephen B. Furber,et al.  Chain: A Delay-Insensitive Chip Area Interconnect , 2002, IEEE Micro.

[12]  Kaamran Raahemifar,et al.  Testing C-elements is not elementary , 1995, Proceedings Second Working Conference on Asynchronous Design Methodologies.

[13]  Ad M. G. Peeters,et al.  Adding synchronous and LSSD modes to asynchronous circuits , 2002, Proceedings Eighth International Symposium on Asynchronous Circuits and Systems.

[14]  Marly Roncken,et al.  The VLSI-programming language Tangram and its translation into handshake circuits , 1991, Proceedings of the European Conference on Design Automation..

[15]  Ad M. G. Peeters,et al.  Stretching quasi delay insensitivity by means of extended isochronic forks , 1995, Proceedings Second Working Conference on Asynchronous Design Methodologies.

[16]  Hans G. Kerkhoff,et al.  Synchronous Full-Scan for Asynchronous Handshake Circuits , 2003, J. Electron. Test..

[17]  Melvin A. Breuer,et al.  Digital Systems Testing & Testable Design , 1993 .

[18]  Alexander Saldanha,et al.  Partial scan delay fault testing of asynchronous circuits , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[19]  Erik Brunvand,et al.  A partial scan methodology for testing self-timed circuits , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[20]  Tom Verhoeff,et al.  Delay-insensitive codes — an overview , 1988, Distributed Computing.

[21]  Hans G. Kerkhoff,et al.  Automatic scan insertion and test generation for asynchronous circuits , 2002, Proceedings. International Test Conference.

[22]  Alexandre Yakovlev,et al.  Self-Timed Control of Concurrent Processes: The Design of Aperiodic Logical Circuits in Computers and Discrete Systems , 1990 .

[23]  Marly Roncken,et al.  Partial scan test for asynchronous circuits illustrated on a DCC error corrector , 1994, Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems.

[24]  Stephen B. Furber,et al.  Scan testing of asynchronous sequential circuits , 1995, Proceedings. Fifth Great Lakes Symposium on VLSI.