High performance DSPs - what's hot and what's not?
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[1] Uming Ko,et al. High performance, energy efficient master-slave flip-flop circuits , 1995, 1995 IEEE Symposium on Low Power Electronics. Digest of Technical Papers.
[2] Hiroshi Kawaguchi,et al. A reduced clock-swing flip-flop (RCSFF) for 63% power reduction , 1998, IEEE J. Solid State Circuits.
[3] Kawaguchi,et al. A Reduced Clock-swing Flip-flop (RCSFF) For 63% Clock Power Reduction , 1997, Symposium 1997 on VLSI Circuits.
[4] Y. Nakagome,et al. Trends in low-power RAM circuit technologies , 1995 .
[5] Earl E. Swartzlander,et al. Low Power Arithmetic Components , 1996 .
[6] Keshab K. Parhi,et al. HEAT: hierarchical energy analysis tool , 1996, DAC '96.
[7] Larsson,et al. Self-adjusting Bit-precision For Low-power Digital Filters , 1997, Symposium 1997 on VLSI Circuits.
[8] Sharad Malik,et al. Power analysis of embedded software: a first step towards software power minimization , 1994, IEEE Trans. Very Large Scale Integr. Syst..
[9] A.P. Chandrakasan. A 1 Mbs energy/security scalable encryption processor using adaptive width and supply , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).
[10] Rob A. Rutenbar,et al. Exploring multiplier architecture and layout for low power , 1996, Proceedings of Custom Integrated Circuits Conference.
[11] Takashi Ishikawa,et al. A low-power design method using multiple supply voltages , 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.
[12] Rajiv Gupta,et al. Low-Power Logic Styles : CMOS vs CPL , 1996, ESSCIRC '96: Proceedings of the 22nd European Solid-State Circuits Conference.
[13] Hirotsugu Kojima,et al. Interlaced accumulation programming for low power DSP , 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.
[14] I. Kuroda,et al. A low-power, 32-bit RISC processor with signal processing capability and its multiply-adder , 1995, VLSI Signal Processing, VIII.
[15] Dan Dobberpuhl. The design of a high performance low power microprocessor , 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.
[16] S.S. Mahant-Shetti,et al. Leap frog multiplier , 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.
[17] L. S. Nielsen,et al. Low-power operation using self-timed circuits and adaptive scaling of the supply voltage , 1994, IEEE Trans. Very Large Scale Integr. Syst..
[18] H. Hanaki,et al. A 2.2 GOPS video DSP with 2-RISC MIMD, 6-PE SIMD architecture for real-time MPEG2 video coding/decoding , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.
[19] H. T. Kung,et al. A Regular Layout for Parallel Adders , 1982, IEEE Transactions on Computers.
[20] Hiroshi Kawaguchi,et al. Low-power CMOS design through VTH control and low-swing circuits , 1997, ISLPED '97.
[21] Amirtharajah,et al. Self-powered Low Power Signal Processing , 1997, Symposium 1997 on VLSI Circuits.
[22] Shin'ichiro Mutoh,et al. 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS , 1995, IEEE J. Solid State Circuits.
[23] Kanad Ghose,et al. Analytical energy dissipation models for low-power caches , 1997, ISLPED '97.
[24] Uming Ko,et al. Low-power design techniques for high-performance CMOS adders , 1995, IEEE Trans. Very Large Scale Integr. Syst..
[25] Rafael Fried. Minimizing energy dissipation in high-speed multipliers , 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.
[26] Wai Lee,et al. Delay balanced multipliers for low power/low voltage DSP core , 1995, 1995 IEEE Symposium on Low Power Electronics. Digest of Technical Papers.
[27] Patrik Larsson,et al. Low power multiplication for FIR filters , 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.
[28] Scott Shenker,et al. Scheduling for reduced CPU energy , 1994, OSDI '94.
[29] Y. Naito,et al. An 800 MOPS 110 mW 1.5 V parallel DSP for mobile multimedia processing , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).