Coding for reliable on-chip buses: a class of fundamental bounds and practical codes

A reliable high-speed bus employing low-swing signaling can be designed by encoding the bus to prevent crosstalk and provide error correction. Coding for on-chip buses requires additional bus wires and codec circuits. In this paper, fundamental bounds on the number of wires required to provide joint crosstalk avoidance and error correction using memoryless codes are presented. The authors propose a code construction that results in practical codec circuits with the number of wires being within 35% of the fundamental bounds. When applied to a 10-mm 32-bit bus in a 0.13-mum CMOS technology with low-swing signaling, one of the proposed codes provides 2.14times speedup and 27.5% energy savings at the cost of 2.1times area overhead, but without any loss in reliability

[1]  M.A. Elgamel,et al.  Interconnect noise analysis and optimization in deep submicron technology , 2003, IEEE Circuits and Systems Magazine.

[2]  Naresh R. Shanbhag,et al.  Coding for systern-on-chip networks: a unified framework , 2004, Proceedings. 41st Design Automation Conference, 2004..

[3]  Mattan Kamon,et al.  FastHenry: A Multipole-Accelerated 3-D Inductance Extraction Program , 1993, 30th ACM/IEEE Design Automation Conference.

[4]  F. Caignet,et al.  The challenge of signal integrity in deep-submicrometer CMOS technology , 2001, Proc. IEEE.

[5]  Srinivasa Raghavan Sridhara.  Communication-Inspired Design of on -Chip Buses , 2006 .

[6]  Naresh R. Shanbhag,et al.  A coding framework for low-power address and data busses , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[7]  Roland W. Freund,et al.  Efficient linear circuit analysis by Pade´ approximation via the Lanczos process , 1994, EURO-DAC '94.

[8]  K. Skadron,et al.  Odd/Even bus invert with two-phase transfer for buses with coupling , 2002, Proceedings of the International Symposium on Low Power Electronics and Design.

[9]  R. Saleh.  FastCap : A Multipole Accelerated 3-D Capacitance Extraction Program , 1991 .

[10]  Sheldon X.-D. Tan,et al.  Wideband passive multiport model order reduction and realization of RLCM circuits , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  O. Brune.  Synthesis of a finite two-terminal network whose driving-point impedance is a prescribed function of frequency , 1931 .

[12]  C. Kyung,et al.  Reducing cross-coupling among interconnect wires in deep-submicron datapath design , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[13]  Igor L. Markov,et al.  Error-correction and crosstalk avoidance in DSM busses , 2004, IEEE Trans. Very Large Scale Integr. Syst..

[14]  Paul-Peter Sotiriadis,et al.  Interconnect modeling and optimization in deep sub-micron technologies , 2002 .

[15]  Kurt Keutzer,et al.  Bus encoding to prevent crosstalk delay , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[16]  Dennis Sylvester,et al.  Analytical modeling and characterization of deep-submicrometer interconnect , 2001 .

[17]  Lawrence T. Pileggi,et al.  RICE: rapid interconnect circuit evaluator , 1991, 28th ACM/IEEE Design Automation Conference.

[18]  Luca Benini,et al.  Low power error resilient encoding for on-chip data buses , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[19]  Guoqing Chen,et al.  An RLC interconnect model based on fourier analysis , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  Chunjie Duan,et al.  Analysis and avoidance of cross-talk in on-chip buses , 2001, HOT 9 Interconnects. Symposium on High Performance Interconnects.

[21]  F. MacWilliams,et al.  The Theory of Error-Correcting Codes , 1977 .

[22]  Dake Liu,et al.  Power consumption estimation in CMOS VLSI chips , 1994, IEEE J. Solid State Circuits.

[23]  Mircea R. Stan,et al.  Bus-invert coding for low-power I/O , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[24]  Naresh R. Shanbhag,et al.  Coding for reliable on-chip buses: fundamental limits and practical codes , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

[25]  Roberto Battiti,et al.  Reactive Local Search for the Maximum Clique Problem1 , 2001, Algorithmica.

[26]  Sung-Mo Kang,et al.  Coupling-driven signal encoding scheme for low-power interface design , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[27]  Lawrence T. Pileggi,et al.  PRIMA: passive reduced-order interconnect macromodeling algorithm , 1997, ICCAD 1997.

[28]  Naresh R. Shanbhag,et al.  A low-power bus design using joint repeater insertion and coding , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

[29]  Andrew B. Kahng,et al.  An analytical delay model for RLC interconnects , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[30]  Janet Roveda,et al.  A new multi-ramp driver model with RLC interconnect load , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[31]  Yehea I. Ismail,et al.  Effects of inductance on the propagation delay and repeater insertion in VLSI circuits , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[32]  Naresh R. Shanbhag,et al.  Toward achieving energy efficiency in presence of deep submicron noise , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[33]  Herbert S. Bennett.  Compound Semiconductor Roadmap Embedded in the 2003 International Technology Roadmap for Semiconductors | NIST , 2004 .

[34]  George Varghese,et al.  Low-swing on-chip signaling techniques: effectiveness and robustness , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[35]  Albert E. Ruehli,et al.  The modified nodal approach to network analysis , 1975 .

[36]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[37]  Wei-Chung Cheng,et al.  Memory bus encoding for low power: a tutorial , 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.

[38]  A. Yang,et al.  Preservation Of Passivity During RLC Network Reduction Via Split Congruence Transformations , 1997, Proceedings of the 34th Design Automation Conference.