Modeling and optimization of semiconductor manufacturing process with neural networks

A neural network-based process model is proposed to optimize the semiconductor manufacturing process. Being different from some works in several research groups which developed neural network-based models to predict process quality with a set of process variables of only single manufacturing step, we applied this model to wafer fabrication parameters control and wafer lot yield optimization. The original data are collected from a wafer fabrication line, including technological parameters and wafer test results. The wafer lot yield is taken as the optimization target. Learning from historical technological records and wafer test results, the model can predict the wafer yield. To eliminate the "bad" or noisy samples from the sample set, an experimental method was used to determine the number of hidden units so that both good learning ability and prediction capability can be obtained.