A novel fault tolerant multiplier using single digit conversion based self checking scheme

Abstract Digital multipliers are key component of all digital signal processing applications. Numerous algorithms and architectures have been proposed to design high-speed and self repairable multipliers for critical applications like space craft and medical applications. This work proposes a self checking scheme for fixed-width array multipliers. The proposed scheme verifies multiply operation by single digit conversion based verification, mainly relying on the use of addition called (MVA) multiplication verification algorithm. To tolerate the fault that occurs in the multiplier circuit, redundancy replicas of multiplier modules are used to replace faulty one. Our proposed multiplier has been implemented using synopsis complier tool, which achieve a low-cost fault-tolerant design when compare with conventional redundancy based error tolerant techniques.