Multi-mode CORDIC processor on a dynamically reconfigurable array

In this paper, an efficient multi-mode CORDIC processing unit is implemented on a dynamically reconfigurable array. The array consists of 4×4 multi-functional Processing Elements (PEs). An efficient pipelined data-flow graph is proposed to implement to achieve a high data throughput and, in the same time, maximizing the resource utilization rate. The implementation results shows that, when compared with the CORDIC IP Core generated by Xilinx ISE design tools, the proposed design achieves a 29% reduction on latency and 6% than the latter, the throughput increased by 29% and 6% than the latter, and it can achieve a considerable precision. Therefore, the proposed design is idea for software-defined radio signal processing systems.

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