A global algorithm for the partial scan design problem using circuit state information

A global partial scan design algorithm based on circuit state information is proposed. Valid states obtained via logic simulation are used to evaluate testability of the circuit. A testability measure based on the density of encoding is used to select scan flip flops, and the problem is formulated into an optimization problem. An algorithm is presented to obtain an initial partial scan design solution, and a variety of techniques are used to subsequently derive an optimal solution. The most significant technique used in the global algorithm is that a dynamic testability measure is adopted, which can greatly reduce the size of the search space and enhance the effectiveness of the search problem. The partial scan design method can greatly reduce potential backtracks during test generation. Experimental results demonstrate 100% test efficiency can be obtained for most circuits selecting fewer scan flip flops than other methods.

[1]  Janak H. Patel,et al.  An optimization based approach to the partial scan design problem , 1990, Proceedings. International Test Conference 1990.

[2]  Spyros Tragoudas,et al.  Partial Scan with Retiming , 1993, 30th ACM/IEEE Design Automation Conference.

[3]  Janak H. Patel,et al.  HITEC: a test generation package for sequential circuits , 1991, Proceedings of the European Conference on Design Automation..

[4]  S. Venkataraman,et al.  Partial scan design based on circuit state information , 1996, 33rd Design Automation Conference Proceedings, 1996.

[5]  Vishwani D. Agrawal,et al.  An exact algorithm for selecting partial scan flip-flops , 1994, 31st Design Automation Conference.

[6]  Kwang-Ting Cheng.  Single-Clock Partial Scan , 1995, IEEE Des. Test Comput..

[7]  K. S. Kim,et al.  Partial scan by use of empirical testability , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[8]  Sujit Dey,et al.  Resynthesis and retiming for optimum partial scan , 1994, DAC '94.

[9]  Kwang-Ting Cheng,et al.  Timing-driven partial scan , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[10]  Janak H. Patel,et al.  A fault oriented partial scan design approach , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[11]  Kewal K. Saluja,et al.  Synthesizing finite state machines for minimum length synchronizing sequence using partial scan , 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[12]  Toshinobu Ono.  Selecting Partial Scan Flip-flops For Circuit Partitioning , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[13]  藤原 秀雄,et al.  Logic testing and design for testability , 1985 .

[14]  Miron Abramovici,et al.  Testability-based partial scan analysis , 1995, J. Electron. Test..

[15]  Janusz Rajski,et al.  Complexity of sequential ATPG , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[16]  Dong Sam Ha,et al.  A new method for partial scan design based on propagation and justification requirements of faults , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[17]  V.D. Agrawal,et al.  Designing circuits with partial scan , 1988, IEEE Design & Test of Computers.

[18]  K.-T. Cheng,et al.  A Partial Scan Method for Sequential Circuits with Feedback , 1990, IEEE Trans. Computers.

[19]  Alan P. Sprague,et al.  Performance of parallel branch-and-bound algorithms , 1985, IEEE Transactions on Computers.

[20]  Sujit Dey,et al.  Resynthesis and Retiming for Optimum Partial Scan , 1994, 31st Design Automation Conference.

[21]  André Ivanov,et al.  Testability Measures : What Do They Do for ATPG ? , 1986, ITC.

[22]  Melvin A. Breuer,et al.  Automatic Design for Testability Via Testability Measures , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[23]  Rabindra K. Roy,et al.  The Best Flip-Flops to Scan , 1991, 1991, Proceedings. International Test Conference.

[24]  David E. Long,et al.  Increasing testability by clock transformation (getting rid of those darn states) , 1996, Proceedings of 14th VLSI Test Symposium.

[25]  Vipin Kumar,et al.  On the Efficiency of Parallel Backtracking , 1993, IEEE Trans. Parallel Distributed Syst..

[26]  S.M. Reddy,et al.  On determining scan flip-flops in partial-scan designs , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[27]  I SantaBarbara.  Single-Clock Partial Scan , 1995 .