TreeFTL: Efficient RAM management for high performance of NAND flash-based storage systems
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[1] Sang Lyul Min,et al. A space-efficient flash translation layer for CompactFlash systems , 2002, IEEE Trans. Consumer Electron..
[2] Tei-Wei Kuo,et al. Joint management of RAM and flash memory with access pattern considerations , 2012, DAC Design Automation Conference 2012.
[3] Hyojun Kim,et al. BPLRU: A Buffer Management Scheme for Improving Random Writes in Flash Storage , 2008, FAST.
[4] Youngjae Kim,et al. DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings , 2009, ASPLOS.
[5] Sooyong Kang,et al. Performance Trade-Offs in Using NVRAM Write Buffer for Flash Memory-Based Storage Devices , 2009, IEEE Transactions on Computers.
[6] Zili Shao,et al. Demand-based block-level address mapping in large-scale NAND flash storage systems , 2010, 2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).
[7] Jin-Soo Kim,et al. An adaptive partitioning scheme for DRAM-based cache in Solid State Drives , 2010, 2010 IEEE 26th Symposium on Mass Storage Systems and Technologies (MSST).
[8] 阿米尔·班. Flash File System , 1994 .
[9] Antony I. T. Rowstron,et al. Write off-loading: Practical power management for enterprise storage , 2008, TOS.
[10] Li-Pin Chang,et al. Plugging versus logging: A new approach to write buffer management for solid-state disks , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).
[11] Zili Shao,et al. A Two-Level Caching Mechanism for Demand-Based Page-Level Address Mapping in NAND Flash Memory Storage Systems , 2011, 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium.
[12] Zili Shao,et al. A block-level flash memory management scheme for reducing write activities in PCM-based embedded systems , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).