Task mapping on NoC-based MPSoCs with faulty tiles: Evaluating the energy consumption and the application execution time

The use of spare tiles in a networks-on-chip based multi-processor chip can improve the yield, reducing the cost of the chip and maintaining the system functionality even if the chip is defective. However, the impact of this approach on application characteristics, such as energy consumption and execution time, is not documented. For instance, on one hand the application tasks might be mapped onto any tile of a defect-free chip. On the other hand, a chip with a defective tile needs special task mapping that avoid fault tiles. This paper presents a task mapping aware of faulty tiles, where an alternative task mapping can be generated and evaluated in terms of energy consumption and execution time. The results show that faults on tiles have, on average, a small effect on energy consumption but no significant effect on execution time. It demonstrates that spare tiles can improve yield with a small impact on the application requirements.

[1]  Vittorio Zaccaria,et al.  Yield enhancement by robust application-specific mapping on network-on-chips , 2009, 2009 2nd International Workshop on Network on Chip Architectures.

[2]  Radu Marculescu,et al.  Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[3]  Qiang Xu,et al.  Energy-efficient task allocation and scheduling for multi-mode MPSoCs under lifetime reliability constraint , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[4]  Fernando Gehm Moraes,et al.  HERMES: an infrastructure for low area overhead packet-switching networks on chip , 2004, Integr..

[5]  Qiang Xu,et al.  Lifetime reliability-aware task allocation and scheduling for MPSoC platforms , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[6]  M.H. Ghadiry,et al.  New approach to calculate energy on NoC , 2008, 2008 International Conference on Computer and Communication Engineering.

[7]  Kwang-Ting Cheng,et al.  Yield and Cost Analysis of a Reliable NoC , 2009, 2009 27th IEEE VLSI Test Symposium.

[8]  Paolo Prinetto,et al.  Reliability in Application Specific Mesh-Based NoC Architectures , 2008, 2008 14th IEEE International On-Line Testing Symposium.

[9]  Sue A Hill,et al.  Chapter 18 – Statistics , 2006 .

[10]  Qiang Xu,et al.  AgeSim: A simulation framework for evaluating the lifetime reliability of processor-based SoCs , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[11]  Petru Eles,et al.  Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[12]  Seung Eun Lee,et al.  A high level power model for Network-on-Chip (NoC) router , 2009, Comput. Electr. Eng..

[13]  B. Mandelbrot.  How Long Is the Coast of Britain? Statistical Self-Similarity and Fractional Dimension , 1967, Science.

[14]  Srinivasan Murali,et al.  Mapping and configuration methods for multi-use-case networks on chips , 2006, Asia and South Pacific Conference on Design Automation, 2006..

[15]  Hokeun Kim,et al.  A task remapping technique for reliable multi-core embedded systems , 2010, 2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[16]  Fernando Gehm Moraes,et al.  HeMPS - a framework for NoC-based MPSoC generation , 2009, 2009 IEEE International Symposium on Circuits and Systems.

[17]  Luca Benini,et al.  Error control schemes for on-chip communication links: the energy-reliability tradeoff , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[18]  Pawel Lewicki,et al.  Statistics : methods and applications : a comprehensive reference for science, industry, and data mining , 2006 .

[19]  Cristinel Ababei,et al.  Achieving network on chip fault tolerance by adaptive remapping , 2009, 2009 IEEE International Symposium on Parallel & Distributed Processing.

[20]  Barruquer Moner.  IX. References , 1971 .

[21]  Fernando Gehm Moraes,et al.  CAFES: A framework for intrachip application modeling and communication architecture design , 2011, J. Parallel Distributed Comput..

[22]  Alain Greiner,et al.  A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[23]  Andrew B. Kahng,et al.  ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[24]  Luca Benini,et al.  Performability/Energy Tradeoff in Error-Control Schemes for On-Chip Networks , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[25]  Juan M. Orduña,et al.  A multi-objective strategy for concurrent mapping and routing in networks on chip , 2009, 2009 IEEE International Symposium on Parallel & Distributed Processing.

[26]  Shashi Kumar,et al.  A two-step genetic algorithm for mapping task graphs to a network on chip architecture , 2003, Euromicro Symposium on Digital System Design, 2003. Proceedings..

[27]  Ahmed Amine Jerraya,et al.  Multiprocessor System-on-Chip (MPSoC) Technology , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.