FPGA Based Efficient Design of Traffic Light Controller using Frequency Scaling for Family of HSTL

Traffic blockage is one of the major issues faced by world today. That can be road traffic or air traffic or even water traffic .Traffic Controllers provide the right direction by providing a rule for any kind of Vehicles. The idea goes around designing traffic light controller system which utilizes least amount of power and is well tested in hardware using Xilinx Virtex6 Field Programmable gate array. FPGA designs are not only cheaper than ASIC designs but have many positive features like speed and performance. So the factors that contribute to power consumption for family of HSTL are studied for the purpose of making Light Controller Efficient using VHDL. Keywords-Traffic Light Controller, ASIC Designs, Virtex6, Speed, Power, HSTL

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