Optimal Linearity Testing of Sigma-Delta Based Incremental ADCs Using Restricted Code Measurements

Linearity testing of high-precision (beyond 20-bit resolution) Analog-to-Digital converters (ADCs) is extremely expensive due to the large number of codes (>16 million for a 24-bit converter) that need to be tested and the associated low data rates making traditional histogram based testing infeasible. Industry often performs linearity test for such high-precision data converters with significantly reduced numbers of code measurements during production test. Given a specified allowed number of code measurements, the problem is to determine the requisite code points that result in the highest failure coverage. In this paper, a methodology and tools for analyzing the "goodness" of a particular choice of test code points versus another is described. A least squares based polynomial fitting approach using measurements made at selected test code points is used to characterize the transfer function of the ADC for INL (Integral Nonlinearity) error. In addition, the characteristics of devices that may escape from the proposed approach (test escapes) are revealed for the specified test via an optimization based search technique. Software simulations are performed to study and validate the proposed methodology.

[1]  Hanjun Jiang,et al.  Testing High-Resolution ADCs With Low-Resolution/Accuracy Deterministic Dynamic Element Matched DACs , 2004, IEEE Transactions on Instrumentation and Measurement.

[2]  G. N. Stenbakken,et al.  Developing linear error models for analog devices , 1993 .

[3]  V. Natarajan,et al.  Testing of High Resolution ADCs Using Lower Resolution DACs via Iterative Transfer Function Estimation , 2009, 2009 14th IEEE European Test Symposium.

[4]  Adoración Rueda,et al.  Simple Evaluation of the Nonlinearity Signature of an ADC Using a Spectral Approach , 2008, VLSI Design.

[5]  Filippo Attivissimo,et al.  FFT test of A/D converters to determine the integral nonlinearity , 2002, IEEE Trans. Instrum. Meas..

[6]  Degang Chen,et al.  Accurate testing of analog-to-digital converters using low linearity signals with stimulus error identification and removal , 2005, IEEE Transactions on Instrumentation and Measurement.

[7]  A. Chatterjee,et al.  Optimal linearity testing of analog-to-digital converters using a linear model , 2003 .

[8]  J. Blair.  Histogram measurement of ADC nonlinearities using sine waves , 1994 .

[9]  R. Geiger,et al.  SEIR Linearity Testing of Precision A/D Converters in Nonstationary Environments With Center-Symmetric Interleaving , 2007, IEEE Transactions on Instrumentation and Measurement.

[10]  Andrea Baschirotto,et al.  Behavioral modeling of switched-capacitor sigma-delta modulators , 2003 .

[11]  Wei Dong,et al.  Achieving Low-Cost Linearity Test and Diagnosis of \Sigma \Delta ADCs via Frequency-Domain Nonlinear Analysis and Macromodeling , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

[12]  J. Doernberg,et al.  Full-speed testing of A/D converters , 1984 .