A Cost-Effective Design for MPEG-2 Audio Decoder with Embedded RISC Core

MPEG-2 audio decoding algorithms are involved of several complex coding techniques and therefore difficult to be implemented by an efficient dedicated architecture design. In this paper, we present an effective architecture for the MPEG-2 audio decoder. The MPEG-2 audio algorithms can be roughly divided into two types of operations. The first type is regular but computation-intensive such as filtering, matrixing, degrouping, and transformation operations. The second type is not regular but computation-intensive such as parsing bitstream, setting operation mode and controlling of all system operations. A RISC core with variable instruction length is designed for the decision-making part, and the dedicated hardware such as special divider, and synthesis filterbank is designed for the computation-intensive part. Based on the standard cell design technique, the VLSI chip consists of 27000 gate counts with the chip size of 6.4 × 6.4 mm2. The chip can run at maximum 43.5 MHz clock rate, with the power dissipation of 150 mW at 3 V power supply.