On Routability for FPGAs under Faulty Conditions

The field programmable gate array (FPGA) routing resources are fixed and their usage is constrained by the location of programmable interconnects (PIs) such as antifuses. The routing or the interconnect delays are determined by the length of segments assigned to the nets of various lengths and the number of PIs programmed for routing of each net. Due to the use of PIs certain unconventional faults may appear. In this paper we model the PI faults and address the design and routability of the FPGA channel architecture to achieve 100% routing with minimum performance penalty in the presence of PI faults. A channel routing algorithm has also been developed which routes nets in the presence of PI faults. Experiments were performed by randomly injecting faults of different types into the routing channel and then using the routing algorithm to determine the routability of the synthesized architecture. Results on a set of industrial designs and MCNC benchmark examples show the feasibility of achieving routability with minimum performance penalty when a large number of faults are present in the channel. >

[1]  C. Stapper.  The effects of wafer to wafer defect density variations on integrated circuit defect and fault distributions , 1985 .

[2]  R. H. Freeman,et al.  A 9000-gate user-programmable gate array , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.

[3]  Robert K. Brayton,et al.  Logic synthesis for programmable gate arrays , 1991, DAC '90.

[4]  Jonathan Rose,et al.  Chortle: a technology mapping program for lookup table-based field programmable gate arrays , 1990, 27th ACM/IEEE Design Automation Conference.

[5]  William S. Carter,et al.  Third-generation architecture boosts speed and density of field-programmable gate arrays , 1990, IEEE Proceedings of the Custom Integrated Circuits Conference.

[6]  C. D. Gelatt,et al.  Optimization by Simulated Annealing , 1983, Science.

[7]  J. Birkner,et al.  A very-high-speed field-programmable gate array using metal-to-metal antifuse programmable elements , 1992 .

[8]  A. El Gamal,et al.  An architecture for electrically configurable gate arrays , 1989 .

[9]  Giovanni De Micheli,et al.  Technology mapping for electrically programmable gate arrays , 1991, 28th ACM/IEEE Design Automation Conference.

[10]  Kaushik Roy,et al.  Channel architecture optimization for performance and routability of row-based FPGAs , 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

[11]  M. Mehendale,et al.  Optimization Of Channel Segmentation For Channelled Architecture FPGAs , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.

[12]  Kevin Karplus.  Amap: a technology mapper for selector-based field-programmable gate arrays , 1991, 28th ACM/IEEE Design Automation Conference.

[13]  L. Cooke,et al.  An MPGA Compatible FPGA Architecture , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.

[14]  Kaushik Roy,et al.  Iterative Wirability and Performance Improvement for FPGAs , 1993, 30th ACM/IEEE Design Automation Conference.

[15]  Huang,et al.  AN EFFICIENT GENERAL COOLING SCHEDULE FOR SIMULATED ANNEALING , 1986 .

[16]  Sinan Kaptanoglu,et al.  Segmented channel routing , 1991, DAC '90.

[17]  A. El Gamal,et al.  FPGA performance versus cell granularity , 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

[18]  Kaushik Roy.  A bounded search algorithm for segmented channel routing for FPGA's and associated channel architecture issues , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..