Designing Analog IC at University of Pavia

The importance and the effectiveness of any actions can be better assessed looking at the long-term results that derived from the original actions associated with it. This is what we are going to see in this paper, where we want to celebrate the research and education activity of Prof. Rinaldo Castello in the Microelectronics Lab at University of Pavia, where all of us have been students starting (in same cases) more than 25 years ago.

[1]  R. Castello,et al.  Wireless multi-standard terminals: system analysis and design of a reconfigurable RF front-end , 2006, IEEE Circuits and Systems Magazine.

[2]  Rinaldo Castello,et al.  A 15 mW, 70 kHz 1/f corner direct conversion CMOS receiver , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[3]  A. Baschirotto,et al.  A 10.7-MHz BiCMOS high-Q double-sampled SC bandpass filter , 1997 .

[4]  R. Castello,et al.  Low-voltage fully differential switched-opamp bandpass /spl Sigma//spl Delta/ modulator , 1999 .

[5]  R. Castello,et al.  High-frequency analog filters in deep-submicron CMOS technology , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[6]  Andrea Baschirotto,et al.  BiCMOS operational amplifier with precise and stable DC gain for high-frequency switched capacitor circuits , 1991 .

[7]  R. Castello,et al.  An innovative modelization of loss mechanism in silicon integrated inductors , 1999 .

[8]  Andrea Baschirotto,et al.  Low-voltage balanced transconductor with high input common-mode rejection , 1994 .

[9]  Andrea Baschirotto,et al.  A 15 MHz 20 mW BiCMOS switched-capacitor biquad operating with 150 Ms/s sampling frequency , 1995 .

[10]  Rinaldo Castello,et al.  SAW-less analog front-end receivers for TDD and FDD , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[11]  A. Baschirotto,et al.  A 200-Ms/s 10-mW switched-capacitor filter in 0.5-/spl mu/m CMOS technology , 2000, IEEE Journal of Solid-State Circuits.

[12]  R. Castello,et al.  A 1 V 1.8 MHz CMOS switched-opamp SC filter with rail-to-rail output swing , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[13]  Rinaldo Castello,et al.  A 70-mW seventh-order filter with 7-50 MHz cutoff frequency and programmable boost and group delay equalization , 1997 .

[14]  Luca Fanori,et al.  A Dither-Less All Digital PLL for Cellular Transmitters , 2012, IEEE Journal of Solid-State Circuits.

[15]  Rinaldo Castello,et al.  A 100-MHz 4-mW four-quadrant BiCMOS analog multiplier , 1997 .

[16]  Andrea Baschirotto,et al.  Design strategy for low-voltage SC circuits , 1994 .

[17]  R. Castello,et al.  A 3V 12-55MHz BiCMOS Continuous-Time Filter with Pseudo-Differential Structure , 1995, ESSCIRC '95: Twenty-first European Solid-State Circuits Conference.

[18]  Andrea Baschirotto.  Considerations for the design of switched-capacitor circuits using precise-gain operational amplifiers , 1996 .

[19]  Andrea Baschirotto,et al.  Finite gain compensated double-sampled switched-capacitor integrators for high-Q bandpass filters , 1992 .

[20]  Andrea Baschirotto,et al.  Tunable BiCMOS continuous-time filter for high-frequency applications , 1992 .

[21]  R. Castello,et al.  An 80MHz 4/spl times/ oversampled cascaded /spl Delta//spl Sigma/-pipelined ADC with 75dB DR and 87dB SFDR , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[22]  R. Castello,et al.  A metal-oxide-semiconductor varactor , 1999, IEEE Electron Device Letters.

[23]  R. Castello,et al.  A 700-kHz bandwidth /spl Sigma//spl Delta/ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications , 2004, IEEE Journal of Solid-State Circuits.