A Parallel Discrete-Event Simulation of Wafer Fabrication Processes

∗ Gintic Institute of Manufacturing, 71 Nanyang Drive, Singapore 639798. Emails: {cclim,yhlow,bpooi,sjain}@gintic.gov.sg # Visiting Researcher, from Department of Computer Science, University of Exeter, Exeter, EX4 4PT, U.K. Email: steve@dcs.exeter.ac.uk + Centre for Advanced Information Systems, School of Applied Science, Nanyang Technological University, Singapore 639798. Emails: { aswtcai,ashsu,assyhuang}@ ntu.edu.sg Abstract Simulation modeling is an important tool for planning factory operations, to identify and eliminate possible bottlenecks and to maintain high machine utili zation. The objective of our project is to apply parallel simulation techniques for virtual factory modeling in the electronics manufacturing sector. We have implemented a parallel wafer fabrication simulation model based on the Sematech data sets [13] . It uses a conservative synchronous protocol [7] modified from [1] , and a static MULTIFIT-COM partitioning scheme [17] to allocate multiple machine sets to logical processes (LP’s). The model, though simplifi ed, does contain certain realistic features found in commercial simulation packages (e.g. TestSim and ManSim [14] .) This paper will give an overview description of our implementation, and show its performance numbers on a 4-CPU Sun Enterprise 3000 system. The preliminary timings demonstrate that, even when the simulated events are relatively fine-grained, it is possible to achieve speedup using a conservative synchronous protocol, with an appropriate partitioning scheme and judicious use of lookahead’s.