A low noise image rejection down CMOS mixer

This paper represents a low noise image rejection mixer in heterodyne architecture for 2 GHz applications based on 0.18 /spl mu/m CMOS technology. The designed mixer uses series inductor and capacitors as a notch filter to suppress the image signal and parasitic capacitance to improve the noise figure (NF) and conversion gain. An image rejection of 20-60 dB is obtained in a 200 MHz of bandwidth around 2 GHz with IF varying from 100 to 300 MHz. The simulation results show single-side band (SSB) NF improved 4 dB, the voltage conversion gain of 14.4 dB, improved by more than 4 dB. The circuit operates at the supply voltage of 1.8 V, and dissipates 11.34 mW.

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