Static and dynamic characterization of GaN HEMT with low inductance vertical phase leg design for high frequency high power applications

In this paper, detailed static characterization of the new 650 V/ 30 A GaN device from GaN Systems is presented. The on-resistance and output capacitance of this device are considerably low making GaN a viable option for high switching frequency (in the range of MHz) medium power applications (> 3 kW). A comprehensive examination of device characteristics and variation of device parasitics depending on operating conditions is presented. Due to the high slew rate of these devices, it is important to incorporate galvanic isolation between gate driver input and output stage as recommended in GaN Systems' application note[1]. Also, the gate loop and power loop stray inductances and capacitances need to be minimized to curtail the switching noise. To achieve this, vertical power loop design with very small parasitic inductance is proposed. The dynamic characterization carried with this design shows reduction of voltage overshoot to less than half compared to the lateral power loop design from [1].