Evaluating SEU and crosstalk effects in network-on-chip routers

This work intends to evaluate the effect of a single event upsets (SEUs) and crosstalk faults in a NoC router architecture by developing a fault injection mechanism, allowing an accurate analysis of the impact of SEU and crosstalk over the router service. Results show that such faults may affect the router behavior, causing loss of packets, errors in packet information or even compromising the router service, provoking permanent routing problems

[1]  Cecilia Metra,et al.  Exploiting ECC redundancy to minimize crosstalk impact , 2005, IEEE Design & Test of Computers.

[2]  Altamiro Amadeu Susin,et al.  SoCIN: a parametric and scalable network-on-chip , 2003, 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings..

[3]  Luigi Carro,et al.  Fault-Tolerance Techniques for SRAM-Based FPGAs (Frontiers in Electronic Testing) , 2006 .

[4]  Luca Benini,et al.  Analysis of error recovery schemes for networks on chips , 2005, IEEE Design & Test of Computers.

[5]  Ricardo P. Jasinski,et al.  Fault-Tolerance Techniques for SRAM-Based FPGAs , 2007, Comput. J..

[6]  Luigi Carro,et al.  Fault-Tolerance Techniques for SRAM-Based FPGAs , 2006 .

[7]  Andrea Acquaviva,et al.  A Bottom-Up Approach to On-Chip Signal Integrity , 2003, PATMOS.

[8]  Cecilia Metra,et al.  Coding techniques for low switching noise in fault tolerant busses , 2005, 11th IEEE International On-Line Testing Symposium.

[9]  M. Nicolaidis,et al.  Design for soft error mitigation , 2005, IEEE Transactions on Device and Materials Reliability.

[10]  Dhiraj K. Pradhan,et al.  IEEE International On-Line Testing Symposium , 2008 .

[11]  Sujit Dey,et al.  Fault modeling and simulation for crosstalk in system-on-chip interconnects , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).