A macromodeling based approach for efficient IC yield optimization

The authors describe a local macromodeling methodology that approximates circuit performance by low-order polynomials in terms of process disturbance variables with coefficients dependent on the designable circuit parameters. The macromodels obtained as a result of a relatively small number of circuit simulations are shown to be useful in predicting circuit yield, yield gradient, and the distribution of circuit performances. The effectiveness of this macromodeling approach is demonstrated in the context of statistical optimization.<<ETX>>