Cache only memory architectures (COMA) have an inherent memory overhead due to the organization of main memory as a large cache called an attraction memory. This overhead consists of memory left unallocated for performance reasons as well as additional physical memory required due to the cache organization of memory. In this work, we examine the effect of data reshuffling and data replication on the memory overhead. Data reshuffling occurs when space needs to be allocated to store a remote memory line in the local memory. Data that is reshuffled is sent between memories via replacement messages. A simple mathematical model predicts the frequency of data reshuffling as a function of the attraction memory parameters. Simulation data shows that the frequency of data reshuffling is sensitive to the allocation policy and associativity of the memory but is relatively unaffected by the block size chosen. The simulation data also shows that data replication in the attraction memory is important for good performance, but most gains can be achieved through replication in the processor caches.
[1]
Erik Hagersten,et al.
DDM - A Cache-Only Memory Architecture
,
1992,
Computer.
[2]
Anoop Gupta,et al.
The directory-based cache coherence protocol for the DASH multiprocessor
,
1990,
ISCA '90.
[3]
Anant Agarwal,et al.
APRIL: a processor architecture for multiprocessing
,
1990,
ISCA '90.
[4]
Anoop Gupta,et al.
Comparative performance evaluation of cache-coherent NUMA and COMA architectures
,
1992,
ISCA '92.
[5]
John L. Hennessy,et al.
The accuracy of trace-driven simulations of multiprocessors
,
1993,
SIGMETRICS '93.
[6]
Anoop Gupta,et al.
SPLASH: Stanford parallel applications for shared-memory
,
1992,
CARN.