Implementation of a low complexity, low power, integer-based turbo decoder

We demonstrate an efficient implementation of a turbo decoder with minor performance loss. The efficient implementation comes from algorithm modification, integer arithmetic, and hardware management. Based on the max-log-MAP decoding algorithm, we modify the branch metrics by weighting a-priori values, resulting in a significant BER improvement. All internal metrics are represented by and operated on integers, avoiding complex calculation seen in floating or fixed-point arithmetic. By careful manipulating hardware, we implement the whole turbo decoder with a single-decoder structure without any interleaving and deinterleaving delay, producing high data throughput with very low logic cell usage. The final FPGA design consumes approximately 650 mW to achieve throughput of more than 1 Mbps. With channel inputs of only 3 bits (8-level), our integer-based turbo decoder results in only 0.25 dB loss of E/sub b//N/sub 0/ from the optimal floating-point turbo decoder.