A Redesign Technique For Combinational Circuits Based On Gate Recomections

In this paper, we consider a redesign technique applicable to combinational circuits implemented with gate-array or standard-cell technology, where we rectify an existing circuit only by reconnecting gates on the circuit with all the gate types unchanged. This constraint allows us to reuse the original placement as is, thereby speeding up the total time needed for a redesign. We formulate this problem as a Boolean-constraint problem and give a BDD-based algorithm to check the feasibility of redesign.

[1]  Robert K. Brayton,et al.  Incremental synthesis for engineering changes , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[2]  Bill Lin,et al.  Minimization of symbolic relations , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[3]  Masahiro Fujita,et al.  Application of Boolean unification to combinational logic synthesis , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[4]  Yahiko Kambayashi,et al.  The Transduction Method-Design of Logic Networks Based on Permissible Functions , 1989, IEEE Trans. Computers.

[5]  Toshihide Ibaraki,et al.  Design of Optimal Switching Networks by Integer Programming , 1972, IEEE Transactions on Computers.

[6]  Masahiro Fujita,et al.  Methods for automatic design error correction in sequential circuits , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[7]  Masahiro Fujita,et al.  Rectification method for lookup-table type FPGA's , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.