Overview of bus-based system-on-chip interconnections
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[1] M. Birnbaum,et al. How VSIA Answers the SOC Dilemma , 1999, Computer.
[2] Russell Tessier,et al. ASOC: a scalable, single-chip communications architecture , 2000, Proceedings 2000 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00622).
[3] Timo Hämäläinen,et al. Reconfiguration mechanism for an IP block based interconnection , 1999, Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium.
[4] Jay K. Strosnider,et al. Modeling bus scheduling policies for real-time systems , 1995, Proceedings 16th IEEE Real-Time Systems Symposium.
[5] William John Bainbridge,et al. Asynchronous macrocell interconnect using MARBLE , 1998, Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems.
[6] B. Cordan. An efficient bus architecture for system-on-chip design , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).
[7] Sujit Dey,et al. Performance analysis of systems with multi-channel communication architectures , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.
[8] Ganesh Lakshminarayana,et al. LOTTERYBUS: a new high-performance communication architecture for system-on-chip designs , 2001, DAC '01.