A SOC test method based on improved RAS architecture

A new random access scan approach is developed to reduce test data volumes,scan power dissipations and test application time.Through improving the RAS scan cell structure,hardware overhead can be reduced,but at the same time test data volumes and test application time can be reduced by the use of the column address signal.Experiments on ISCAS'89 benchmark circuits have shown an average reduction of 55% in test data volumes and an average reduction of 52% in the test application time compared with the serial scan method;meanwhile,the average test power dissipations can be ignored.