Highly scalable sub-50nm vertical double gate trench DRAM cell

Results of a highly scalable 8F2 DRAM cell are presented. For the first time the fabrication of a fully depicted vertical transistor DRAM is demonstrated. Based on extensive process and device simulations, the scalability of the proposed cell beyond the 50nm DRAM node is highlighted.

[1]  U. Gruening,et al.  A novel trench DRAM cell with a vertical access transistor and buried strap (VERI BEST) for 4 Gb/16 Gb , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[2]  W. Bergner,et al.  A highly cost efficient 8F/sup 2/ DRAM cell with a double gate vertical transistor device for 100 nm and beyond , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[3]  S. Slesazeck,et al.  Fully depleted surrounding gate transistor (SGT) for 70 nm DRAM and beyond , 2002, Digest. International Electron Devices Meeting,.

[4]  D. Kim,et al.  The breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor(RCAT) for 88 nm feature size and beyond , 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).