Low power discrete voltage assignment under clock skew scheduling
暂无分享,去创建一个
Li Li | Yinghai Lu | Hai Zhou | Xuan Zeng | Jian Sun
[1] Evangeline F. Y. Young,et al. Multi-voltage floorplan design with optimal voltage assignment , 2009, ISPD '09.
[2] Hung-Yi Liu,et al. Voltage Island Aware Floorplanning for Power and Timing Optimization , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.
[3] Charlie Chung-Ping Chen,et al. Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation , 2005, ASP-DAC.
[4] I-Min Liu,et al. Timing-constrained and voltage-island-aware voltage assignment , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[5] Yao-Wen Chang,et al. An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.
[6] Evangeline F. Y. Young,et al. Network flow-based power optimization under timing constraints in MSV-driven floorplanning , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.
[7] David Blaauw,et al. Discrete Vt assignment and gate sizing using a self-snapping continuous formulation , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..
[8] Charlie Chung-Ping Chen,et al. Fast and effective gate-sizing with multiple-V/sub t/ assignment using generalized Lagrangian relaxation , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..
[9] Hai Zhou,et al. Efficient algorithms for buffer insertion in general circuits based on network flow , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..
[10] M. Dessouky,et al. Solving the Project Time/Cost Tradeoff Problem Using the Minimal Cut Concept , 1977 .
[11] Seda Ogrenci Memik,et al. Leakage power-aware clock skew scheduling: Converting stolen time into leakage power reduction , 2008, 2008 45th ACM/IEEE Design Automation Conference.
[12] John M. Cohn,et al. Managing power and performance for system-on-chip designs using Voltage Islands , 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..
[13] H. Zhou,et al. Gate Sizing by Lagrangian Relaxation Revisited , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[14] Yu Wang,et al. Simultaneous slack budgeting and retiming for synchronous circuits optimization , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).
[15] Dorit S. Hochbaum,et al. Solving the Convex Cost Integer Dual Network Flow Problem , 1999, Manag. Sci..
[16] Yao-Wen Chang,et al. An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning , 2007, ICCAD 2007.
[17] Gerhard J. Woeginger,et al. Hardness of approximation of the discrete time-cost tradeoff problem , 2001, Oper. Res. Lett..
[18] Shiyan Hu,et al. The epsilon-approximation to discrete VT assignment for leakage power minimization , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.
[19] Klaus Jansen,et al. Approximation algorithms for general packing problems and their application to the multicast congestion problem , 2008, Math. Program..
[20] Martin Skutella,et al. Approximation Algorithms for the Discrete Time-Cost Tradeoff Problem , 1997, Math. Oper. Res..
[21] Prabuddha De,et al. Complexity of the Discrete Time-Cost Tradeoff Problem for Project Networks , 1997, Oper. Res..