High performance dual-output second and third generation current conveyors and current-mode multifunction filter application

A wide bandwidth CMOS realization of high performance dual output second generation (CCII±) and third generation (CCIII±) current conveyors are presented. Both second and third generation current conveyors have the advantages of a wide current and voltage bandwidths, controlled intrinsic resistances at port X, Y and Z. We have developed an optimization program, thanks to Heuristic methodology that is used for optimal sizing regarding static and dynamic performance. PSPICE simulation show that the current and voltage bandwidths are respectively 1.5806 GHz and 6.506 GHz, and 454.11 Ω as RX input port resistance for a control current of 100 µA. CCII± is a useful building block for analog circuits, especially for application requiring dual outputs. The proposed circuit is able of operating at voltage supply (±2.5V), with reduced power consumption. A frequency characterization of the proposed CCII± is given, this CCII± is characterized by low values for its parasitic input resistance (454.11 Ω). In this paper, we present a versatile multi-input multi-output controlled filter configuration. Either a three-input single output or single-input double-output universal filter can be realized. The proposed circuits offer the following advantageous features: realization of current-mode low-pass and band-pass filter responses from the same configuration, employing only three current conveyors and four grounded passive elements. In order to implement a current controlled Radiofrequency active filter, we use a translinear configuration for both second and third generation current conveyors. The proposed implementation exhibiting a current controlled intrinsic resistances at port X, Y and Z allow a control of the cut-off frequency. The cut-off frequency of the low pass filter can be attend 1.64 GHz and the central frequency of the band pass filter can be attend 1.13 GHz. Simulation results are in good accordance with theoretical ones. PSPICE simulations using CMOS 0.35µm technology parameters are performed to demonstrate the results.

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