Testing 3-D IC Through-Silicon-Vias (TSVs) by Direct Probing

Testing the integrity of interconnects realized by through silicon vias (TSVs) in 3-D integrated circuits (3-D IC) is considered a challenging task. TSVs are excessively small and fragile for current probe technology. In this paper, a new spring-type probe using microelectromechanical systems (MEMS) technology is presented. The implemented MEMS probe supports the required pitch for TSV direct probing and minimizes the undesired scrub marks on TSV surface. Simulation results indicate that the implemented MEMS probe can operate at the gigahertz frequency range without significant test signal degradation.

[1]  H. Koeppen,et al.  Alloys C17400 and C17410-New Beryllium Copper Alloys for Connector Applications , 1986 .

[2]  R. Timsit The potential distribution in a constricted cylinder , 1977 .

[3]  Mark Nakamoto,et al.  Impact of thinning and packaging on a deep submicron CMOS product , 2009 .

[4]  M. Puech,et al.  Fabrication of 3D packaging TSV using DRIE , 2008, 2008 Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS.

[5]  M.B. Steer,et al.  Design for 3D Integration and Applications , 2007, 2007 International Symposium on Signals, Systems and Electronics.

[6]  Yervant Zorian,et al.  Testing 3D chips containing through-silicon vias , 2009, 2009 International Test Conference.

[7]  Ding-Ming Kwai,et al.  On-chip testing of blind and open-sleeve TSVs for 3D IC before bonding , 2010, 2010 28th VLSI Test Symposium (VTS).

[8]  Jian-Qiang Lu,et al.  Modeling Thermal Stresses in 3-D IC Interwafer Interconnects , 2006, IEEE Transactions on Semiconductor Manufacturing.

[9]  B. Dang,et al.  3D silicon integration , 2008, 2008 58th Electronic Components and Technology Conference.

[10]  Lin Fu,et al.  High throughput non-contact SiP testing , 2007, 2007 IEEE International Test Conference.

[11]  Jian Xu,et al.  Demystifying 3D ICs: the pros and cons of going vertical , 2005, IEEE Design & Test of Computers.

[12]  Hsien-Hsin S. Lee,et al.  A scanisland based design enabling prebond testability in die-stacked microprocessors , 2007, 2007 IEEE International Test Conference.

[13]  William R. Mann,et al.  The leading edge of production wafer probe test technology , 2004, 2004 International Conferce on Test.

[14]  Eby G. Friedman,et al.  Electrical modeling and characterization of 3-D vias , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[15]  Ilko Schmadlak,et al.  Damage risk assessment of under-pad structures in vertical wafer probe technology , 2009, 2009 European Microelectronics and Packaging Conference.

[16]  Sung Kyu Lim,et al.  Design method and test structure to characterize and repair TSV defect induced signal degradation in 3D system , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[17]  Raymond F. Wegman,et al.  Copper and Copper Alloys , 2013 .

[18]  Prabhakar Goel,et al.  Electronic Chip-In-Place Test , 1982, 19th Design Automation Conference.

[19]  M. Beiley,et al.  A micromachined array probe card-fabrication process , 1995 .

[20]  William H. Kautz,et al.  Testing for Faults in Wiring Networks , 1974, IEEE Transactions on Computers.

[21]  Ding-Ming Kwai,et al.  On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification , 2009, 2009 Asian Test Symposium.

[22]  I K Yanson,et al.  Point-contact Spectroscopy of Metals , 1988 .

[23]  Luca Benini,et al.  A low-overhead fault tolerance scheme for TSV-based 3D network on chip links , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[24]  B. Kaminska,et al.  Oscillation-test strategy for analog and mixed-signal integrated circuits , 1996, Proceedings of 14th VLSI Test Symposium.

[25]  Qiang Xu,et al.  Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[26]  F. L. Jones Electric Contacts , 1947, Nature.

[27]  Peter Ramm,et al.  Handbook of 3D integration : technology and applications of 3D integrated circuits , 2012 .

[28]  Eric Beyne,et al.  Electrically yielding Collective Hybrid Bonding for 3D stacking of ICs , 2009, 2009 59th Electronic Components and Technology Conference.

[29]  A. Jourdain,et al.  3D stacked IC demonstration using a through Silicon Via First approach , 2008, 2008 IEEE International Electron Devices Meeting.

[30]  E. Beyne,et al.  3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias , 2006, 2006 International Electron Devices Meeting.

[31]  J. Greenwood Constriction resistance and the real area of contact , 1966 .

[32]  H. Murray Characterization of copper-beryllium alloy C17510 , 1991, [Proceedings] The 14th IEEE/NPSS Symposium Fusion Engineering.

[33]  P. Wyder,et al.  Point-Contact Spectroscopy in a Heavy-Fermion Metal: UPt3 vs Cu , 1988 .

[34]  S. Das,et al.  Fabrication technologies for three-dimensional integrated circuits , 2002, Proceedings International Symposium on Quality Electronic Design.

[35]  Robert S. Patti,et al.  Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs , 2006, Proceedings of the IEEE.

[36]  Mitsumasa Koyanagi,et al.  Handbook of 3D Integration , 2008 .

[37]  D. Malta,et al.  Integrated process for defect-free copper plating and chemical-mechanical polishing of through-silicon vias for 3D interconnects , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[38]  Krishnendu Chakrabarty,et al.  Testing and Design-for-Testability Techniques for 3D Integrated Circuits , 2011, 2011 Asian Test Symposium.

[39]  A. Jourdain,et al.  Through-silicon via and die stacking technologies for microsystems-integration , 2008, 2008 IEEE International Electron Devices Meeting.