A 10-b 500 MSPS current-steering CMOS D/A converter with a self-calibrated current biasing technique

A 10-b 500 MSPS current-steering CMOS digital-to-analog converter with internal termination resistors is presented. In order to improve the device-mismatching problem of internal termination resistors, a self-calibrated current bias circuit is designed. With the self-calibrated current bias circuit, the gain error of the output voltage swing is reduced within 0.5%. Further, for the purpose of reducing glitch noise, a novel current switch based on a deglitching circuit is proposed. A 10-b CMOS DAC has been fabricated with a 3 V, 0.35 /spl mu/m technology, and it consumes 45 mW. The measured SFDR (spurious free dynamic range) is about 65 dB, when the input signal is about 8 MHz at 500 MHz clock frequency.

[1]  A. Fraval,et al.  A 10-bit 70 MHz 3.3 V CMOS 0.5 /spl mu/m D/A converter for video applications , 1995 .

[2]  Bang-Sup Song,et al.  A self-trimming 14-b 100-MS/s CMOS DAC , 2000, IEEE Journal of Solid-State Circuits.

[3]  Michel Steyaert,et al.  A 12-bit intrinsic accuracy high-speed CMOS DAC , 1998, IEEE J. Solid State Circuits.

[4]  D. Mercer,et al.  A 16-b D/A converter with increased spurious free dynamic range , 1994, IEEE J. Solid State Circuits.

[5]  W. Sansen,et al.  A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter , 2001, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

[6]  Georges Gielen,et al.  A 14-bit intrinsic accuracy Q2 random walk CMOS DAC , 1999, IEEE J. Solid State Circuits.