Hierarchical defect-oriented fault simulation for digital circuits

A new fault model is developed for estimating the coverage of physical defects in digital circuits for given test sets. Based on this model, a new hierarchical defect oriented fault simulation method is proposed. At the higher level simulation we use the functional fault model, at the lower level we use the defect/fault relationships in the form of defect coverage table and the defect probabilities. A description and the experimental data are given about probabilistic analysis of a complex CMOS gate. Analysis of the quality of 100% stuck-at fault test sets for two benchmark circuits in covering physical defects like internal shorts, stuck-opens and stuck-ons. It has been shown that in the worst case a test with 100% stuck-at fault coverage may, have only 50% coverage for internal shorts in complex CMOS gates. It has been shown that classical test coverage calculation based on counting defects without taking into account the defect probabilities may lead to considerable overestimation of results.

[1]  John Paul Shen,et al.  Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells , 1984, ITC.

[2]  Alfredo Benso,et al.  A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[3]  Wojciech Maly,et al.  Layout-driven test generation , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[4]  Wojciech Maly,et al.  Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Witold A. Pleskacz,et al.  Estimation of Probability of Different Functional Faults Caused by Spot Defects in VLSI Circuits , 2000 .

[6]  J. R. Armstrong,et al.  Hierarchical test generation for VHDL behavioral models , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[7]  Elizabeth M. Rudnick,et al.  Fast sequential circuit test generation using high-level and gate-level techniques , 1998, Proceedings Design, Automation and Test in Europe.

[8]  John Paul Shen,et al.  Inductive Fault Analysis of MOS Integrated Circuits , 1985, IEEE Design & Test of Computers.

[9]  Marcel Jacomet,et al.  Layout-dependent fault analysis and test synthesis for CMOS circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Charles F. Hawkins,et al.  Quality testing requires quality thinking , 1993, Proceedings of IEEE International Test Conference - (ITC).