A DRAM/SRAM memory scheme for fast packet buffers

We address the design of high-speed packet buffers for Internet routers. We use a general DRAM/SRAM architecture for which previous proposals can be seen as particular cases. For this architecture, large SRAMs are needed to sustain high line rates and a large number of interfaces. A novel algorithm for DRAM bank allocation is presented that reduces the SRAM size requirements of previously proposed schemes by almost an order of magnitude, without having memory fragmentation problems. A technological evaluation shows that our design can support thousands of queues for line rates up to 160 Gbps.

[1]  Jonathan S. Turner,et al.  WDM burst switching for petabit capacity routers , 1999, MILCOM 1999. IEEE Military Communications. Conference Proceedings (Cat. No.99CH36341).

[2]  Mark J. Karol.  Shared-memory optical packet (ATM) switch , 1993, Optics & Photonics.

[3]  George N. Glykopoulos.  Design and Implementation of a 1.2 Gbit/s ATM Cell Buffer using a Synchronous DRAM chip , 1998 .

[4]  R. Spanke,et al.  Architectures for large nonblocking optical space switches , 1986 .

[5]  Rajiv Ramaswami,et al.  Optical Networks , 1998 .

[6]  Nick McKeown,et al.  Scaling internet routers using optics , 2003, SIGCOMM '03.

[7]  Russ White,et al.  Inside Cisco IOS Software Architecture , 2000 .

[8]  Cheng-Shang Chang,et al.  Load balanced Birkhoff-von Neumann switches, part I: one-stage buffering , 2002, Computer Communications.

[9]  Jonathan S. Turner,et al.  Terabit burst switching , 1999, J. High Speed Networks.

[10]  François Koeune.  Pseudo-random number generator , 2005, Encyclopedia of Cryptography and Security.

[11]  GambiniP.,et al.  Transparent optical packet switching , 2006 .

[12]  Eduard Ayguadé,et al.  Increasing the number of strides for conflict-free vector access , 1992, ISCA '92.

[13]  M. March,et al.  On the design of hybrid DRAM/SRAM memory schemes for fast packet buffers , 2004, 2004 Workshop on High Performance Switching and Routing, 2004. HPSR..

[14]  B. Ramakrishna Rau,et al.  The Cydram 5 Stride-Insensitive Memory System , 1989, ICPP.

[15]  Abhay Parekh,et al.  A generalized processor sharing approach to flow control in integrated services networks: the multiple node case , 1994, TNET.

[16]  Abhay Parekh,et al.  A generalized processor sharing approach to flow control in integrated services networks: the single-node case , 1993, TNET.

[17]  Eduard Ayguadé,et al.  Conflict-Free Access for Streams in Multimodule Memories , 1995, IEEE Trans. Computers.

[18]  Biswanath Mukherjee,et al.  Some principles for designing a wide-area WDM optical network , 1996, TNET.

[19]  Mateo Valero,et al.  A conflict-free memory banking architecture for fast VOQ packet buffers , 2003, GLOBECOM '03. IEEE Global Telecommunications Conference (IEEE Cat. No.03CH37489).

[20]  Mateo Valero,et al.  Design and Implementation of High-Performance Memory Systems for Future Packet Buffers , 2003, MICRO.

[21]  Monique Renaud,et al.  Transparent optical packet switching: The European ACTS KEOPS project approach , 1998, 1999 IEEE LEOS Annual Meeting Conference Proceedings. LEOS'99. 12th Annual Meeting. IEEE Lasers and Electro-Optics Society 1999 Annual Meeting (Cat. No.99CH37009).

[22]  David T. Harper,et al.  Performance Evaluation of Vector Accesses in Parallel Memories Using a Skewed Storage Scheme , 1986, ISCA.

[23]  Fouad A. Tobagi,et al.  Provisioning internet backbone networks to support latency sensitive applications , 2002 .

[24]  Chunming Qiao,et al.  Optical burst switching: a new area in optical networking research , 2004, IEEE Netw..

[25]  Nick McKeown,et al.  Part I: buffer sizes for core routers , 2005, CCRV.

[26]  Ivan Andonovic,et al.  SLOB: a switch with large optical buffers for packet switching , 1998 .

[27]  Ivan Andonovic,et al.  Buffering in optical packet switches , 1998 .

[28]  Richard Crisp,et al.  Direct RAMbus technology: the new main memory standard , 1997, IEEE Micro.

[29]  Norman P. Jouppi,et al.  Cacti 3. 0: an integrated cache timing, power, and area model , 2001 .

[30]  Imrich Chlamtac,et al.  Lightpath (Wavelength) Routing in Large WDM Networks , 1996, IEEE J. Sel. Areas Commun..

[31]  M. Valero,et al.  Design and implementation of high-performance memory systems for future packet buffers , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[32]  Rodney S. Tucker,et al.  Wavelength routing-based photonic packet buffers and their applications in photonic packet switching systems , 1998 .

[33]  Manolis Katevenis,et al.  Efficient per-flow queueing in DRAM at OC-192 line rate using out-of-order execution techniques , 2001, ICC 2001. IEEE International Conference on Communications. Conference Record (Cat. No.01CH37240).

[34]  Guido Appenzeller,et al.  Sizing router buffers , 2004, SIGCOMM '04.

[35]  Mateo Valero,et al.  Command vector memory systems: high performance at low cost , 1998, Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192).

[36]  Richard V. Penty,et al.  WASPNET: a wavelength switched packet network , 1999, IEEE Commun. Mag..

[37]  Nick McKeown,et al.  A load-balanced switch with an arbitrary number of linecards , 2004, IEEE INFOCOM 2004.

[38]  T. N. Vijaykumar,et al.  Efficient use of memory bandwidth to improve network processor throughput , 2003, ISCA '03.

[39]  Salim Tariq,et al.  Next generation DWDM networks: demands, capabilities and limitations , 2000, 2000 Canadian Conference on Electrical and Computer Engineering. Conference Proceedings. Navigating to a New Era (Cat. No.00TH8492).

[40]  Hao Jiang,et al.  Buffer sizing for congested Internet links , 2005, Proceedings IEEE 24th Annual Joint Conference of the IEEE Computer and Communications Societies..

[41]  Y. Tamir,et al.  High-performance multi-queue buffers for VLSI communications switches , 1988, ISCA '88.

[42]  Christoph M. Gauger,et al.  Evaluation of Reservation Mechanisms for Optical Burst Switching , 2001 .

[43]  Martin May,et al.  Aggregate traffic performance with active queue management and drop from tail , 2001, CCRV.

[44]  Chunming Qiao,et al.  Optical burst switching (OBS) - a new paradigm for an Optical Internet^{1} , 1999, J. High Speed Networks.

[45]  Cheng-Shang Chang,et al.  Load balanced Birkhoff-von Neumann switches , 2001, 2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552).

[46]  Cheng-Shang Chang,et al.  Load balanced Birkhoff-von Neumann switches, part II: multi-stage buffering , 2002, Comput. Commun..

[47]  Cyriel Minkenberg,et al.  Current issues in packet switch design , 2003, CCRV.