Adaptive Voltage Frequency Scaling Using Critical Path Accumulator Implemented in 28nm CPU
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Samuel Naffziger | Stephen Kosonocky | Aaron Grenat | Sriram Sundaram | Michael Golden | Sriram Sambamurthy | Michael Austin
[1] A.J. Drake,et al. Dynamic measurement of critical-path timing , 2008, 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial.
[2] R.W. Brodersen,et al. A dynamic voltage scaled microprocessor system , 2000, IEEE Journal of Solid-State Circuits.
[3] David Blaauw,et al. Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[4] David M. Bull,et al. RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance , 2009, IEEE Journal of Solid-State Circuits.
[5] Bishop Brock,et al. Active management of timing guardband to save energy in POWER7 , 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[6] Dave Johnson,et al. 4.8 A 28nm x86 APU optimized for power and area efficiency , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.