A Fully CMOS Low-Cost Chaotic Neural Network

A chaotic IC is proposed and fabricated using a 0.35 mum CMOS technology. The circuit iterates an N-shaped transfer function that can be modified using two external voltages, and is implemented using a three neurons network. The main advantages of the proposed circuit are based on its simplicity, small area (47 times 57 mum2), and its MOS-only implementation requiring no more than 15 MOS transistors. Measurements show the suitability of the proposed system to reproduce a chaotic signal and to be used as a random number generator.

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