Industrial experience with adoption of edt for low-cost test without concessions

This paper discusses the adoption of Embedded Deterministic Test (EDT) at InJineon Technologies as a means to reduce the cost of manufacturing test without compromising test quality. The System-onChip (SoC) design flow and the changes necessary to successfully implement EDT are presented. Experimental results for three SoC designs targeted for automotive, wireless, and data communication applications are provided. These results demonstrate that EDT, with no performance impact, little area overhead, and minimal impact to theflow, results in a signijicant reduction of scan test data volume and scan test time while maintaining the test quality levels.

[1]  Nur A. Touba,et al.  Test vector encoding using partial LFSR reseeding , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[2]  Sreejit Chakravarty,et al.  Experimental evaluation of scan tests for bridges , 2002, Proceedings. International Test Conference.

[3]  Subhasish Mitra,et al.  X-compact: an efficient response compaction technique for test cost reduction , 2002, Proceedings. International Test Conference.

[4]  Brion L. Keller,et al.  Extending OPMISR beyond 10x Scan Test Efficiency , 2002, IEEE Des. Test Comput..

[5]  Jacob Savir,et al.  Built In Test for VLSI: Pseudorandom Techniques , 1987 .

[6]  Peter C. Maxwell.  Wafer/package test mix for optimal defect detection , 2002, Proceedings. International Test Conference.

[7]  B. Koenemann.  LFSR-coded test patterns for scan designs , 1991 .

[8]  カッサブ，マーク,et al.  Test pattern compression method for an integrated circuit test environment , 2000 .

[9]  B. Koneman,et al.  LFSR-Coded Test Patterns for Scan Designs , 1993 .

[10]  P. Muhmenthaler.  Cost effective testing of systems on silicon: areas for optimization , 1999, European Test Workshop 1999 (Cat. No.PR00390).

[11]  Janusz Rajski,et al.  High speed ring generators and compactors of test data [logic IC test] , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[12]  Alex Orailoglu,et al.  Test volume and application time reduction through scan chain concealment , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[13]  Xijiang Lin,et al.  Test generation for designs with multiple clocks , 2003, DAC '03.

[14]  Navid Shahriari,et al.  Realizing the benefits of structural test for Intel microprocessors , 2002, Proceedings. International Test Conference.

[15]  Janusz Rajski,et al.  Decompression of test data using variable-length seed LFSRs , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[16]  Nilanjan Mukherjee,et al.  Embedded deterministic test for low cost manufacturing test , 2002, Proceedings. International Test Conference.

[17]  S. Hellebrand,et al.  An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).