A 10-mW 3.6-Gbps I/O transmitter

This paper describes a low-power self-terminated transmitter. A novel architecture is proposed to perform impedance matching and channel equalization with low power consumption. The test chip is fabricated using 0.18-/spl mu/m digital CMOS process with 1.8-V supply. The transmitter operates at 3.6 Gbps and consumes 9.66 mW. The total transmitter area is 0.072 mm/sup 2/.

[1]  W.J. Dally,et al.  Low-power area-efficient high-speed I/O circuit techniques , 2000, IEEE Journal of Solid-State Circuits.

[2]  D. Inglis,et al.  A CMOS low-power multiple 2.5-3.125-Gb/s serial link macrocellfor high IO bandwidth network ICs , 2002, IEEE Journal of Solid-State Circuits.