A programmable BIST for DRAM testing and diagnosis

This paper proposes a programmable Built-In Self-Test (BIST) approach for DRAM test and diagnosis. The proposed architecture suits well for embedded core testing as well as for stacked and stand-alone DRAMs and it provides programmability features for executing both March and NPSF-oriented test algorithms. The proposed BIST structure is designed to be easily customized with memory topology parameters such as scrambling and mirroring, in order to automatically adapt the test circuitry to the specific memory design. Experimental results show that area overhead is negligible when considering medium-large memory cuts, while executing at-speed and Back-to-Back algorithms at more than 1GHz.

[1]  Rubin A. Parekhji,et al.  Built-in self-test technique for selective detection of neighbourhood pattern sensitive faults in memories , 2004, 17th International Conference on VLSI Design. Proceedings..

[2]  Cheng-Wen Wu,et al.  A Programmable BIST Core for Embedded DRAM , 1999, IEEE Des. Test Comput..

[3]  Chung-Fu Lin,et al.  Single-instruction based programmable memory BIST for testing embedded DRAM , 2009, 2009 International Symposium on VLSI Design, Automation and Test.

[4]  Ad J. van de Goor,et al.  Disturb neighborhood pattern sensitive fault , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[5]  Andrea Costa,et al.  Programmable memory BIST , 2005, IEEE International Conference on Test, 2005..

[6]  Sungju Park,et al.  A microcode-based memory BIST implementing modified march algorithm , 2001, Proceedings 10th Asian Test Symposium.

[7]  R. E. Abdel-Aal,et al.  Generic DFT approach for pattern sensitive faults in word-oriented memories , 1996 .

[8]  Vishwani D. Agrawal,et al.  Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits [Book Review] , 2000, IEEE Circuits and Devices Magazine.

[9]  Dipanwita Roy Chowdhury,et al.  A programmable built-in self-test for embedded DRAMs , 2005, 2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05).

[10]  Cheng-Wen Wu,et al.  Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Bruce F. Cockburn,et al.  Synthesized transparent BIST for detecting scrambled pattern-sensitive faults in RAMs , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[12]  A. J. van de Goor,et al.  Testing Semiconductor Memories: Theory and Practice , 1998 .

[13]  Ad J. van de Goor,et al.  An overview of deterministic functional RAM chip testing , 1990, CSUR.

[14]  Kozo Kinoshita,et al.  Design of a BIST RAM with row/column pattern sensitive fault detection capability , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[15]  P. Mazumder,et al.  An efficient built-in self testing for random-access memory , 1989 .

[16]  Sungho Kang,et al.  A parallel test algorithm for pattern sensitive faults in semiconductor random access memories , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

[17]  Hoon Chang,et al.  An extended march test algorithm for embedded memories , 1997, Proceedings Sixth Asian Test Symposium (ATS'97).

[18]  Yiorgos Tsiatouhas,et al.  New test pattern generation units for NPSF oriented memory built-in self test , 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

[19]  Ad J. van de Goor,et al.  Address and data scrambling: causes and impact on memory tests , 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002.