Low-power and high-speed VLSI architecture for lifting-based forward and inverse wavelet transform

A low-power, high-speed architecture which performs two-dimension forward and inverse discrete wavelet transform (DWT) for the set of filters in JPEG2000 is proposed by using a line-based and lifting scheme. It consists of one row processor and one column processor each of which contains four sub-filters. And the row processor which is time-multiplexed performs in parallel with the column processor. Optimized shift-add operations are substituted for multiplications, and edge extension is implemented by an embedded circuit. The whole architecture which is optimized in the pipeline design way to speed up and achieve higher hardware utilization has been demonstrated in FPGA. Two pixels per clock cycle can be encoded at 100 MHz. The architecture can he used as a compact and independent IP core for JPEG2000 VLSI implementation and various real-time image/video applications.

[1]  Wim Sweldens,et al.  Lifting scheme: a new philosophy in biorthogonal wavelet constructions , 1995, Optics + Photonics.

[2]  Chaitali Chakrabarti,et al.  A VLSI architecture for lifting-based forward and inverse wavelet transform , 2002, IEEE Trans. Signal Process..

[3]  Chen-Yi Lee,et al.  A line-based, memory efficient and programmable architecture for 2D DWT using lifting scheme , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[4]  S. Srinivasan,et al.  VLSI implementation of 2-D DWT/IDWT cores using 9/7-tap filter banks based on the non-expansive symmetric extension scheme , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[5]  I. Daubechies,et al.  Factoring wavelet transforms into lifting steps , 1998 .

[6]  David S. Taubman,et al.  High performance scalable image compression with EBCOT , 1999, Proceedings 1999 International Conference on Image Processing (Cat. 99CH36348).

[7]  Mary Jane Irwin,et al.  VLSI architectures for the discrete wavelet transform , 1995 .

[8]  G. Knowles.  VLSI architecture for the discrete wavelet transform , 1990 .

[9]  Jean-Didier Legat,et al.  Combined line-based architecture for the 5-3 and 9-7 wavelet transform of JPEG2000 , 2003, IEEE Trans. Circuits Syst. Video Technol..

[10]  Touradj Ebrahimi,et al.  Christopoulos: Thc Jpeg2000 Still Image Coding System: an Overview the Jpeg2000 Still Image Coding System: an Overview , 2022 .