Implication logic gates using spin-transfer-torque-operated magnetic tunnel junctions for intrinsic logic-in-memory

Abstract As the feature size of CMOS components scales down, the standby power losses due to high leakage currents have become a top concern for modern circuit design. Introducing non-volatility in logic circuits allows to overcome the standby power issue. Magnetic tunnel junctions (MTJs) offer a great potential, because of their non-volatility, unlimited endurance, CMOS compatibility, and fast switching speed. This work proposes current- and voltage-controlled MTJ-based implication (IMP) logic gtes for future non-volatile logic-in-memory architecture. The MTJ-based implication logic realizes an intrinsic logic-in-memory known as “stateful” logic for which the MTJ devices serve simultaneously as memory elements and logic gates. Spintronic implication logic gates are analyzed by using a SPICE model for spin-transfer torque (STT) MTJs in order to show the reliability of the IMP operation. It has been demonstrated that the proposed current-controlled implication gate offers a higher performance (power and reliability) than the conventional voltage-controlled one. The realization of the spintronic stateful logic operations extends non-volatile electronics from memory to logical computing applications and opens the door for more complex logic functions to be realized with MTJ-based devices. We present a stateful logic circuit based on the common STT-MRAM architecture capable of performing material implication. As an application example, an IMP-based implementation of a full-adder is presented.